公开(公告)号：EP2171586B1

公开(公告)日：2013-05-08

申请号：EP08760760.2

申请日：2008-06-10

申请人： International Business Machines Corporation

发明人： ALVES, Luiz ,  CLARKE, William ,  DELL, Timothy ,  DEWKETT, Thomas ,  GOWER, Kevin ,  LASTRAS-MONTANO, Luis ,  O`CONNOR, James

IPC分类号： G06F11/10

CPC分类号： G06F11/108 ,  G06F2211/1045 ,  G06F2211/1057 ,  G06F2211/1064

公开(公告)号：EP1628225A3

公开(公告)日：2008-11-05

申请号：EP05106701.5

申请日：2005-07-21

申请人： International Business Machines Corporation

发明人： DELL, Timothy ,  GOWER, Kevin ,  KARK, Kevin ,  KELLOGG, Mark ,  MAULE, Warren

IPC分类号： G06F13/16 ,  G06F13/42

CPC分类号： G06F13/4243 ,  G06F13/1684

摘要： A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.

公开(公告)号：EP2171586A2

公开(公告)日：2010-04-07

申请号：EP08760760.2

申请日：2008-06-10

申请人： International Business Machines Corporation

发明人： ALVES, Luiz ,  CLARKE, William ,  DELL, Timothy ,  DEWKETT, Thomas ,  GOWER, Kevin ,  LASTRAS-MONTANO, Luis ,  O`CONNOR, James

IPC分类号： G06F11/10

CPC分类号： G06F11/108 ,  G06F2211/1045 ,  G06F2211/1057 ,  G06F2211/1064

摘要： A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.

公开(公告)号：EP1628225A2

公开(公告)日：2006-02-22

申请号：EP05106701.5

申请日：2005-07-21

申请人： International Business Machines Corporation

发明人： DELL, Timothy ,  GOWER, Kevin ,  KARK, Kevin ,  KELLOGG, Mark ,  MAULE, Warren

IPC分类号： G06F13/16 ,  G06F13/42

CPC分类号： G06F13/4243 ,  G06F13/1684

摘要： A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.

摘要翻译： 一个用于提供总线速度倍增器的存储器子系统。 存储器子系统包括以存储器模块数据速率操作的一个或多个存储器模块。 存储器子系统还包括存储器控制器和一个或多个存储器总线。 存储器总线的存储器模块数据速率是四倍。 存储器控制器和存储器模块通过分组化的多传输接口经由存储器总线互连。