公开(公告)号：EP2389688B1

公开(公告)日：2018-12-05

申请号：EP10701251.0

申请日：2010-01-27

申请人： International Business Machines Corporation

发明人： RASSEL, Robert, Mark ,  ANDERSON, Frederick, Gustav ,  ZIERAK, Michael, Joseph ,  COLLINS, David ,  PHELPS, Richard

IPC分类号： H01L29/808 ,  H01L21/337 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

CPC分类号： H01L29/1058 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/808

摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

公开(公告)号：EP2389688A1

公开(公告)日：2011-11-30

申请号：EP10701251.0

申请日：2010-01-27

申请人： International Business Machines Corporation

发明人： RASSEL, Robert, Mark ,  ANDERSON, Frederick, Gustav ,  ZIERAK, Michael, Joseph ,  COLLINS, David ,  PHELPS, Richard

IPC分类号： H01L29/808 ,  H01L21/337 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

CPC分类号： H01L29/1058 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/808

摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff / Vpinch.

摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。