公开(公告)号：EP4421873A1

公开(公告)日：2024-08-28

申请号：EP24152278.8

申请日：2024-01-17

申请人： GlobalFoundries U.S. Inc.

发明人： PANDEY, Shesh Mani ,  KRISHNASAMY, Rajendran ,  TAN, Chung Foong

IPC分类号： H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/336 ,  H01L29/40

CPC分类号： H01L29/7835 ,  H01L29/4983 ,  H01L29/66659 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/517 ,  H01L29/407

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a device with workfunction metal in a drift region and methods of manufacture. The structure includes: a gate structure having at least a first workfunction metal in a channel region and a second workfunction metal, which is different from the first workfunction metal, in a trench in a drift region; and a sidewall spacer adjacent to the gate structure within the trench in the drift region.

公开(公告)号：EP4404269A1

公开(公告)日：2024-07-24

申请号：EP23192844.1

申请日：2023-08-23

申请人： GlobalFoundries U.S. Inc.

发明人： Pandey, Shesh Mani ,  Krishnasamy, Rajendran

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659

摘要： Disclosed are embodiments of a semiconductor structure including a semiconductor device with an active device region and, within the active device region, porous semiconductor material adjacent to an isolation structure. In some embodiments, the semiconductor device can be a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET). The LDMOSFET can include an active device region, a well region within the active device region and, within the well region, an isolation structure, a porous region immediately adjacent to the isolation structure, and a drain drift region that borders the isolation structure (e.g., between a channel region and a drain region). The porous region can modify the electric field in the drain drift region around the isolation structure and, as a result, can improve both drain-to-source breakdown voltage (BVdss) and transconductance (Gm) of the device. Also disclosed are method embodiments for forming the semiconductor structure.

公开(公告)号：EP4391081A1

公开(公告)日：2024-06-26

申请号：EP23218845.8

申请日：2023-12-20

申请人： Commissariat à l'énergie atomique et aux énergies alternatives

发明人： BARRAUD, Sylvain ,  COQUAND, Rémi ,  REBOH, Shay

IPC分类号： H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L21/336 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/45 ,  H01L29/775 ,  H01L29/16

CPC分类号： H01L29/0673 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/778 ,  B82Y10/00 ,  H01L29/45 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/1606 ,  H01L29/0653 ,  H10B53/30 ,  H10B12/03 ,  H10B12/05 ,  H01L29/78696

摘要： Dispositif microélectronique (100) comprenant :
- une couche de semi-conducteur (120) semi-conductrice dont plusieurs premières zones (122) sont superposées et forment un canal ;
- une grille de commande électrostatique (110) et une couche (112) de diélectrique de grille ou une couche (112) mémoire ferroélectrique dont des parties soient chacune disposée entre une partie (106, 108) de la grille et l'une des premières zones ;
- des espaceurs diélectriques (114) disposés contre des flancs de la grille ;
- des régions de source (116) / drain (118) couplées électriquement aux premières zones par des deuxièmes zones (124) de la couche de semi-conducteur s'étendant entre les régions de source / drain et les espaceurs, et/ou entre un substrat (102) et chacune des régions de source / drain ;
et dans lequel les deuxièmes zones ne sont pas disposées directement contre la grille et forment, avec les premières zones, une couche continue.

公开(公告)号：EP3935737B1

公开(公告)日：2024-05-29

申请号：EP20709582.9

申请日：2020-03-09

IPC分类号： H03K17/06 ,  H01L29/40 ,  H01L29/66

CPC分类号： H03K17/06 ,  H03K2017/06620130101 ,  H03K2217/001820130101 ,  H01L29/407 ,  H01L29/7813 ,  H01L29/0634 ,  H01L29/0653

公开(公告)号：EP4080582B1

公开(公告)日：2024-04-24

申请号：EP22169177.7

申请日：2022-04-21

IPC分类号： H01L29/778 ,  H01L29/417 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/0619 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/0653

公开(公告)号：EP2629320B1

公开(公告)日：2018-10-17

申请号：EP13155361.2

申请日：2013-02-15

申请人： IMEC VZW

发明人： Vincent, Benjamin ,  Thean, Aaron ,  Witters, Liesbeth

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L23/04 ,  H01L25/04 ,  H01L29/66 ,  C30B19/00 ,  C30B23/04 ,  C30B25/04 ,  C30B29/40

CPC分类号： H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

摘要： The invention is related to a mask structure suitable for producing a defect free epitaxially grown structure of a crystalline material on substrate of another crystalline material, the two materials having difference lattice constants. The mask comprises two levels : a first level comprising a first layer provided with a first opening, for example of first trench, the bottom of which is formed by the substrate formed of the first material. The second level comprises at least a barrier placed on at least two opposite sides of the trench. According to a preferred embodiment, the second level comprises one or more second trenches arranged perpendicularly to the first trench. The depth and width of the first and second trenches is such that defects generated in the epitaxially grown layer of the second material at the substrate portion at the bottom of the first trench, and propagating in the direction of the second trenches are trapped in the first trench. In this way, in the larger portion of the second trenches, essentially defect free material can be grown.

公开(公告)号：EP3324444A1

公开(公告)日：2018-05-23

申请号：EP17201514.1

申请日：2017-11-14

申请人： Renesas Electronics Corporation

发明人： Mori, Takahiro

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/336

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device according to one embodiment includes a semiconductor substrate (SUB) having a first surface (FS), an insulating isolation structure (ISL) having a first depth (D1), and a gate electrode (GE). The semiconductor substrate has source and drain regions (SR, DRA), a reverse conductivity region (RCR) having a second depth (D2), a body region (BR), and a drift region (DRI). The source region, the drift region, and the drain region are of a first conductivity type, and the body region and the reverse conductivity region are of a second conductivity type which is opposite to the first conductivity type. The insulating isolation structure is disposed between the drain region and the reverse conductivity region. The first depth is larger than the second depth.

公开(公告)号：EP3314641A1

公开(公告)日：2018-05-02

申请号：EP15896571.5

申请日：2015-06-26

申请人： Intel Corporation

发明人： MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  GHANI, Tahir ,  METZ, Matthew V.

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66522 ,  B82Y10/00 ,  H01L21/02395 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30612 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

摘要： A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

公开(公告)号：EP3311400A1

公开(公告)日：2018-04-25

申请号：EP15895835.5

申请日：2015-06-19

申请人： Intel Corporation

发明人： YANG, Xiaodong ,  LIN, Jui-Yen ,  PHOA, Kinyip ,  NIDHI, Nidhi ,  CHEN, Yi Wei ,  SHIH, Kun-huan ,  HAFEZ, Walid M. ,  TSAI, Curtis

IPC分类号： H01L21/60

CPC分类号： H01L29/7813 ,  H01L23/481 ,  H01L29/0653 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/945

摘要： A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.

公开(公告)号：EP3288069A1

公开(公告)日：2018-02-28

申请号：EP17186343.4

申请日：2017-08-16

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： ZHOU, Fei

IPC分类号： H01L21/8234 ,  H01L29/66

CPC分类号： H01L21/823481 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/517 ,  H01L29/66545

摘要： Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an isolation layer in the base substrate; forming dummy gate structures on the base substrate at two sides of the isolation layer; forming an additional gate structure on the isolation layer and a first protective layer on surfaces of the additional gate structure and the dummy gate structures; forming an interlayer dielectric layer covering side surfaces of the dummy gate structures, the additional gate structure and the first protective layer over the base substrate; removing a portion of the first protective layer over the additional gate structure; forming a second protective layer on the additional gate structure; removing portions of the first protective layer over the dummy gate structures using the second protective layer as a mask; and removing the dummy gate structures to form openings in the interlayer dielectric layer.

摘要翻译： 提供半导体器件及其制造方法。 示例性制造方法包括提供基础衬底; 在基底中形成隔离层; 在所述隔离层的两侧在所述衬底基板上形成伪栅极结构; 在所述隔离层上形成附加栅极结构，并且在所述附加栅极结构和所述伪栅极结构的表面上形成第一保护层; 形成覆盖所述虚设栅极结构，所述附加栅极结构和所述第一保护层在所述基底衬底之上的侧表面的层间介电层; 去除附加栅极结构上的第一保护层的一部分; 在附加栅极结构上形成第二保护层; 使用所述第二保护层作为掩模去除所述伪栅极结构上的所述第一保护层的部分; 以及去除伪栅极结构以在层间介电层中形成开口。