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11 条记录 (耗时 0.016 秒)

    Instruction fetch control system in a computer and method for controlling the computer
    4.
    发明公开
    Instruction fetch control system in a computer and method for controlling the computer 失效
    计算机中的指令FETCH控制系统和用于控制计算机的方法

    公开(公告)号：EP0013291A3

    公开(公告)日：1980-10-01

    申请号：EP79103615

    申请日：1979-09-24

    申请人： International Business Machines Corporation

    发明人： Berglund, Neil Clair ,  Crowley, Richard Douglas ,  Kempke, William George ,  Richardson, William Cain

    IPC分类号： G06F09/06 ,  G06F13/00

    CPC分类号： G06F9/3017 ,  G06F9/268 ,  G06F9/30145 ,  G06F9/30181

    摘要： An I-fetch control system for a computer includes a control store (30) for storing end op, 1-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next micro-instruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to 1-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to 1-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (30) to being E-phase.

    Data processing apparatus with memory access protection
    7.
    发明公开
    Data processing apparatus with memory access protection 失效
    Datenverarbeitungsgerätmit Speicherzugangsschutz。

    公开(公告)号：EP0010190A2

    公开(公告)日：1980-04-30

    申请号：EP79103604.9

    申请日：1979-09-24

    申请人： International Business Machines Corporation

    发明人： Aberle, Gary Francis ,  Balm, Gerald John ,  Berstis, Viktors ,  Gregg, Leon Edward ,  Hu, Kuang-Chi ,  Richardson, William Cain ,  Schardt, Terry Lyle ,  Ranweiler, James Gregory ,  Watson, Charles Thomas

    IPC分类号： G06F13/00

    CPC分类号： G06F9/52

    摘要： In a multitasking restricted access data processing system a common compact mechanism is provided for resolving access conflicts automatically irrespective of the category of restriction (read access, modify access or destroy access the type of restriction (shared or exclusive) or the origin of the restriction (user specified or instruction implied). The mechanism operates by testing codewords (34) totally defining the access restriction in relation to a newly required access and currently in force access restrictions in relation to the inhabitants of a chained list (24) associated by a hashed object address form (18) access being denied, held pending until released or a time-out exception occurs or granted, the list appropriate to the transaction being updated accordingly and also updated as restrictions are released.

    摘要翻译： 在多任务限制访问数据处理系统中，提供了一种共同的紧凑机制，用于自动解决访问冲突，而不管限制踏板访问的类别，修改访问或销毁访问; 限制（限制（指定用户或指令隐含））的限制（共享或排他）的类型。 该机制通过测试相关于新的所需访问和相对于由散列对象地址形式（18）访问相关联的链表（24）的居民的当前有效访问限制来完全定义访问限制的码字（34） 被拒绝，等待直到发布或超时异常发生或授予，适当的交易的列表被相应地更新，并且在限制被释放时更新。

    Apparatus and method for background memory test during system start up
    8.
    发明公开
    Apparatus and method for background memory test during system start up 失效
    Gerätund Verfahren zur Background-Speicherprüfungwährenddes Systemanlaufs。

    公开(公告)号：EP0442651A2

    公开(公告)日：1991-08-21

    申请号：EP91300946.0

    申请日：1991-02-05

    申请人： International Business Machines Corporation

    发明人： Cheng, Chingshun ,  Porter, Scott Lyon ,  Richardson, William Cain ,  Roy, Paul Julius

    IPC分类号： G11C29/00 ,  G06F11/22

    CPC分类号： G06F11/2284 ,  G06F11/2273 ,  G11C29/08

    摘要： A system and method is provided for testing a computer system main memory during system startup. An initial block of memory (20) is tested and marked as valid or invalid during a startup sequence, with the remaining system memory initially marked as bad. An operating system and applications can be loaded into the initial block and operate normally, and a concurrent process is invoked to test the remaining system memory. This allows the remaining system memory to be tested and marked as valid during normal system operation.

    摘要翻译： 提供了一种用于在系统启动期间测试计算机系统主存储器的系统和方法。 初始的存储器块（20）在启动序列期间被测试并标记为有效或无效，其余的系统存储器最初被标记为坏。 可以将操作系统和应用程序加载到初始块中并正常运行，并且调用并发进程来测试剩余的系统内存。 这允许剩余的系统存储器在正常系统操作期间被测试并被标记为有效。

    Instruction fetch control system in a computer
    9.
    发明公开
    Instruction fetch control system in a computer 失效
    电子计算机中的Stefeersystemfürden Befehlsabruf。

    公开(公告)号：EP0013291A2

    公开(公告)日：1980-07-23

    申请号：EP79103615.5

    申请日：1979-09-24

    申请人： International Business Machines Corporation

    发明人： Berglund, Neil Clair ,  Crowley, Richard Douglas ,  Kempke, William George ,  Richardson, William Cain

    IPC分类号： G06F9/06 ,  G06F13/00

    CPC分类号： G06F9/3017 ,  G06F9/268 ,  G06F9/30145 ,  G06F9/30181

    摘要： An I-fetch control system for a computer includes a control store (30) for storing end op, 1-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next micro-instruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to 1-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to 1-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (30) to being E-phase.

    摘要翻译： 用于计算机的取指控制系统包括用于存储结束操作，I-1，I-2和返回字的控制存储器（30）。 微指令解码和控制单元（170）响应终端操作词来初始化和个性化计算机组件以便于后续执行高级指令。 控制单元（170）结合下一个地址逻辑（162），响应于高电平指令选择要执行的下一个@微指令@。 控制单元（170）和逻辑（162）响应于I-1个字以个性化计算机并选择微指令以开始高电平指令的E相。 响应于I-2控制字，控制单元（170）和逻辑（162）在控制存储器（30）中选择操作数提取例程，并将第一E阶地址写入本地存储器（138）。 返回字从本地存储器（138）门控第一个E相地址，以将控制存储器（30）中的微指令选择为E相。