Instruction fetch control system in a computer
    3.
    发明公开
    Instruction fetch control system in a computer 失效
    电子计算机中的Stefeersystemfürden Befehlsabruf。

    公开(公告)号:EP0013291A2

    公开(公告)日:1980-07-23

    申请号:EP79103615.5

    申请日:1979-09-24

    IPC分类号: G06F9/06 G06F13/00

    摘要: An I-fetch control system for a computer includes a control store (30) for storing end op, 1-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next micro-instruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to 1-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to 1-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (30) to being E-phase.

    摘要翻译: 用于计算机的取指控制系统包括用于存储结束操作,I-1,I-2和返回字的控制存储器(30)。 微指令解码和控制单元(170)响应终端操作词来初始化和个性化计算机组件以便于后续执行高级指令。 控制单元(170)结合下一个地址逻辑(162),响应于高电平指令选择要执行的下一个@微指令@。 控制单元(170)和逻辑(162)响应于I-1个字以个性化计算机并选择微指令以开始高电平指令的E相。 响应于I-2控制字,控制单元(170)和逻辑(162)在控制存储器(30)中选择操作数提取例程,并将第一E阶地址写入本地存储器(138)。 返回字从本地存储器(138)门控第一个E相地址,以将控制存储器(30)中的微指令选择为E相。

    Computer instruction prefetch circuit
    4.
    发明公开
    Computer instruction prefetch circuit 失效
    命令预先充电为数据处理系统电路。

    公开(公告)号:EP0010188A1

    公开(公告)日:1980-04-30

    申请号:EP79103602.3

    申请日:1979-09-24

    IPC分类号: G06F9/38

    CPC分类号: G06F9/3814 G06F9/3802

    摘要: A digital computer system includes a computation unit (14), a main store (12), TVirtual address translator (10), a microinstruction control unit (170) and an instruction code prefetch circuit (212). User instruction codes are stored sequentially in the main store (12) which is accessed for read and write operations by the virtual address translator (10). The instruction code prefetch circuit (212) retrieves the user instruction codes from the main store (12) and holds the instruction codes in a register (16,18). The instruction codes are transferred from the register (16,18) to the computation unit (14) in sequential order of use. The microinstruction control unit (170) produces selected microinstructions which are executed by the computation unit (14) to accomplish the operations specified by the user instructions. Designated microinstructions include commands which activate the instruction code prefetch circuit (212) to retrieve the succeeding user instruction codes from the main store (12).

    Instruction fetch control system in a computer and method for controlling the computer
    8.
    发明公开
    Instruction fetch control system in a computer and method for controlling the computer 失效
    计算机中的指令FETCH控制系统和用于控制计算机的方法

    公开(公告)号:EP0013291A3

    公开(公告)日:1980-10-01

    申请号:EP79103615

    申请日:1979-09-24

    IPC分类号: G06F09/06 G06F13/00

    摘要: An I-fetch control system for a computer includes a control store (30) for storing end op, 1-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next micro-instruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to 1-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to 1-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (30) to being E-phase.

    Computer system including a task handling apparatus
    10.
    发明公开
    Computer system including a task handling apparatus 失效
    Einen Apparat zur Aufgabenbehandlung enthaltendes Computersystem。

    公开(公告)号:EP0021146A2

    公开(公告)日:1981-01-07

    申请号:EP80103084.2

    申请日:1980-06-03

    IPC分类号: G06F9/46 G06F3/04

    摘要: The specification concerns a task handling apparatus for a computer system where the task dispatcher is selectively operable under instruction control for performing task queue selection and where the intertask communication mechanism can return a task dispatching element (TDE) to a non-prime task dispatching queue (TDQ) as well as to the prime TDQ. Whenever a TDE is returned to the prime TDQ, the task dispatcher makes a pre-emptive task switch. Also, if there are no task dispatching elements on the current non-prime TDQ, the task dispatcher switches to dispatch TDE's from the prime TDQ.

    摘要翻译: 该规范涉及用于计算机系统的任务处理装置,其中任务调度器在指令控制下选择性地可操作以执行任务队列选择,并且其中任务间通信机制可以将任务调度元素(TDE)返回到非主要任务分派队列 TDQ)以及主要TDQ。 每当TDE返回到主要的TDQ时,任务分派器就会先行执行任务切换。 此外,如果当前非主要TDQ上没有任务调度元素,任务调度员将切换到从主要TDQ发送TDE。