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公开(公告)号：EP0035646B1
公开(公告)日：1988-11-02
申请号：EP81100811.9
申请日：1981-02-05
CPC分类号： G11C11/34 , G11C11/40 , G11C11/56 , G11C11/5692
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公开(公告)号：EP0035646A3
公开(公告)日：1983-08-03
申请号：EP81100811
申请日：1981-02-05
CPC分类号： G11C11/34 , G11C11/40 , G11C11/56 , G11C11/5692
摘要： A storage system, such as a read only memory, is provided which includes field effect transistors (54, 56) each having first and second spaced apart diffusion regions (38,40; 46, 48) of a given conductivity and a gate electrode (28,30), with at least one of the two diffusion regions of selected transistors having a third diffusion (42,44) adjacent to one of the first and second diffusion regions (38, 40; 46,48) under the gate electrodes (28, 30) to provide a higher voltage threshold for the gate electrode to one diffusion than for the gate electrode to the other of the two diffusions. A voltage is applied to the first diffusion (38) having a polarity and magnitude sufficient to neutralize or eliminate the effects of the higher threshold during a first time period and the current flowing between the first and second diffusions (38,40; 46,48) is sensed. During a second period of time the voltage is applied to the second diffusion (46, 48) and the current flow between the first and second diffusions (38, 40; 46, 48) is again sensed. In this manner two cells or bits of information are stored in each transistor (54, 56), one at the first diffusion (38) and one at the second diffusion (48). Multilevel storing may also be employed by establishing one of more than two predetermined voltage thresholds at each of the first and second diffusions.
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公开(公告)号：EP0035646A2
公开(公告)日：1981-09-16
申请号：EP81100811.9
申请日：1981-02-05
CPC分类号： G11C11/34 , G11C11/40 , G11C11/56 , G11C11/5692
摘要： A storage system, such as a read only memory, is provided which includes field effect transistors (54, 56) each having first and second spaced apart diffusion regions (38,40; 46, 48) of a given conductivity and a gate electrode (28,30), with at least one of the two diffusion regions of selected transistors having a third diffusion (42,44) adjacent to one of the first and second diffusion regions (38, 40; 46,48) under the gate electrodes (28, 30) to provide a higher voltage threshold for the gate electrode to one diffusion than for the gate electrode to the other of the two diffusions. A voltage is applied to the first diffusion (38) having a polarity and magnitude sufficient to neutralize or eliminate the effects of the higher threshold during a first time period and the current flowing between the first and second diffusions (38,40; 46,48) is sensed. During a second period of time the voltage is applied to the second diffusion (46, 48) and the current flow between the first and second diffusions (38, 40; 46, 48) is again sensed. In this manner two cells or bits of information are stored in each transistor (54, 56), one at the first diffusion (38) and one at the second diffusion (48). Multilevel storing may also be employed by establishing one of more than two predetermined voltage thresholds at each of the first and second diffusions.
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