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    Logic circuit test probe
    5.
    发明公开
    Logic circuit test probe 失效
    Probesondefürlogische Schaltung。

    公开(公告)号：EP0182388A2

    公开(公告)日：1986-05-28

    申请号：EP85114975.7

    申请日：1982-04-28

    申请人： JOHN FLUKE MFG. CO., INC.

    发明人： Bhaskar, Kasi Seshadri c/o John Fluke Mfg Co. Ltd. ,  Carlson, Alden J. ,  Couper, Alastair Norman ,  Lambert, Dennis L. ,  Scott, Marshall H.

    IPC分类号： G01R31/28

    CPC分类号： G06F11/261 ,  G01R19/16557 ,  G01R31/31912 ,  G06F11/2221 ,  G06F11/2257 ,  G06F11/2273 ,  G06F11/2736 ,  G06F11/32 ,  G06F11/325

    摘要： 0 A test probe includes an electrode (162) for contacting a circuit node of the logic circuit being tested. The signal from the electrode is passed to first and second comparators (166, 168) which compare the signal with acceptable high and low threshold voltages for the type of logic circuitry being tested. In this way, a visual indication can be given that the logic level of the monitored circuit node is high, low, invalid, or is a sequence of pulses of all three logic levels. The test probe also provides for injection of logical high pulses, logical low pulses or an alternating pulse of high and low pulses. Probe level detection and pulse injection can be asynchronous or selectively synchronized so that logic level detection or pulse injection occurs with each unit under test write or read operation.

    摘要翻译： 测试探针包括用于接触被测逻辑电路的电路节点的电极（162）。 来自电极的信号被传递到第一和第二比较器（166,168），该比较器将信号与可接受的高和低阈值电压进行比较，用于所测试的逻辑电路的类型。 以这种方式，可以看出所监视的电路节点的逻辑电平高，低，无效或是所有三个逻辑电平的脉冲序列的视觉指示。 测试探针还提供逻辑高脉冲，逻辑低脉冲或高脉冲和低脉冲交替脉冲的注入。 探头电平检测和脉冲注入可以是异步或选择性同步，以便在每个待测单元写入或读取操作时发生逻辑电平检测或脉冲注入。

    Kernel testing interface and method for automating diagnostics of microprocessor-based systems
    6.
    发明公开
    Kernel testing interface and method for automating diagnostics of microprocessor-based systems 失效
    基于微处理器的系统的KERNEL测试界面和自动诊断方法

    公开(公告)号：EP0370929A3

    公开(公告)日：1991-08-28

    申请号：EP89420462.7

    申请日：1989-11-22

    申请人： JOHN FLUKE MFG. CO., INC.

    发明人： Polstra, John D. ,  White, Bruce T. ,  Scott, Marshall H.

    IPC分类号： G06F11/22

    CPC分类号： G06F11/261 ,  G06F11/277

    摘要： An improved testing apparatus and method for testing the kernel of a microprocessor based unit under test (UUT) where connection to the UUT is made at both the memory connection socket and at the microprocessor with the microprocessor being in place and active in the UUT. The apparatus and method permits subtantially full diagnostics of the kernel to be carried out in a systematic and automated manner in which the requirement of manual probing of the UUT is minimized. Connections at the microprocessor permit the development of high resolution sync signals for verification and evaluation of test results and permit testing without latching of signals on the data bus. The testing protocol implemented in the methodincludes the use of testing primitives which permit the development of a signature for each address and data bus line for the identification of the type as well as the location of any faults discovered by the apparatus. The method of testing exploits bootstrapping techniques including three primitives for bus test, data stimulus and address stimulus to optimize simultaneous testing and circuit fault diagnosis.

    Kernel testing interface and method for automating diagnostics of microprocessor-based systems
    7.
    发明公开
    Kernel testing interface and method for automating diagnostics of microprocessor-based systems 失效
    Kern-Prüfschnittstelleund Verfahren zur Diagnostikautomatisierung mikroprozessor-betriebener Systeme。

    公开(公告)号：EP0370929A2

    公开(公告)日：1990-05-30

    申请号：EP89420462.7

    申请日：1989-11-22

    申请人： JOHN FLUKE MFG. CO., INC.

    发明人： Polstra, John D. ,  White, Bruce T. ,  Scott, Marshall H.

    IPC分类号： G06F11/22

    CPC分类号： G06F11/261 ,  G06F11/277

    摘要： An improved testing apparatus and method for testing the kernel of a microprocessor based unit under test (UUT) where connection to the UUT is made at both the memory connection socket and at the microprocessor with the microprocessor being in place and active in the UUT. The apparatus and method permits subtantially full diagnostics of the kernel to be carried out in a systematic and automated manner in which the requirement of manual probing of the UUT is minimized. Connections at the microprocessor permit the development of high resolution sync signals for verification and evaluation of test results and permit testing without latching of signals on the data bus. The testing protocol implemented in the methodincludes the use of testing primitives which permit the development of a signature for each address and data bus line for the identification of the type as well as the location of any faults discovered by the apparatus. The method of testing exploits bootstrapping techniques including three primitives for bus test, data stimulus and address stimulus to optimize simultaneous testing and circuit fault diagnosis.

    摘要翻译： 一种用于测试基于微处理器的被测单元（UUT）的内核的改进的测试装置和方法，其中在UUT的存储器连接插座和微处理器处连接到UUT，微处理器在UUT中就位并且处于活动状态。 该装置和方法允许以系统和自动化的方式对要进行的UUT的手动探测的要求进行基本的完全诊断。 微处理器的连接允许开发高分辨率同步信号，用于验证和评估测试结果，并允许在数据总线上不锁定信号的情况下进行测试。 在该方法中实现的测试协议包括使用允许为每个地址和数据总线生成签名的测试原语，用于识别该类型以及该设备发现的任何故障的位置。 测试方法利用引导技术，包括用于总线测试，数据刺激和地址激励的三个原语，以优化同时测试和电路故障诊断。

    A test system for functionally testing a microprocessor-based assembly, and apparatus for testing logic circuitry
    8.
    发明公开
    A test system for functionally testing a microprocessor-based assembly, and apparatus for testing logic circuitry 失效
    一种测试系统，用于测试基于微型计算机布置和装置的功能进行测试的电路。

    公开(公告)号：EP0067510A2

    公开(公告)日：1982-12-22

    申请号：EP82302172.0

    申请日：1982-04-28

    申请人： JOHN FLUKE MFG. CO., INC.

    发明人： Bhaskar, Kasi Seshadri ,  Carlson, Alden J. ,  Couper, Alastair Norman ,  Lambert, Dennis L. ,  Scott, Marshall H.

    IPC分类号： G06F11/26 ,  G01R31/28

    CPC分类号： G06F11/261 ,  G01R19/16557 ,  G01R31/31912 ,  G06F11/2221 ,  G06F11/2257 ,  G06F11/2273 ,  G06F11/2736 ,  G06F11/32 ,  G06F11/325

    摘要： AA microprocessor-based test system for functionally testing and troubleshooting microprocessor-based systems is connected in place of the microprocessor circuit of the unit 18 being tested (UUT). The test system includes a microprocessor circuit 42 which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT 18. The test system periodically switches this microprocessor 42 into signal communication with the UUT 18 for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit 42 is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/0 registers 26, 28 and 30.

    摘要翻译： 为功能性测试和故障排除基于微处理器的系统被连接到位单元18的微处理器电路的基于微处理器的测试系统进行测试（UUT）。 该测试系统包括被提供与所述UUT时钟信号，并作为由所述UUT 18的测试系统，定期此微处理器42切换到信号通信中与UUT 18用于单个使用的相同类型的微处理器电路的微处理器电路42的所有 UUT总线周期执行UUT读或写操作。 在剩余的时间周期中，测试系统微处理器电路42是在与测试系统先前UUT写入期间分析从UUT总线获得的数据或读取操作和建立信号的剩余部分进行信号通信中的下一个要使用的 UUT读或写操作。 被提供用于测试UUT总线，RAM，ROM中的各种测试序列，和写入响应I / O寄存器26，28和30号