公开(公告)号：EP0615251B1

公开(公告)日：2001-08-16

申请号：EP94100019.2

申请日：1994-01-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Ohsawa, Takashi, c/o Intellectual Property Div. ,  Fujii, Shuso, c/o Intellectual Property Div.

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C29/08 ,  G11C29/24 ,  G11C29/34 ,  G11C29/40 ,  G11C29/44

公开(公告)号：EP0615251A3

公开(公告)日：1997-02-12

申请号：EP94100019.2

申请日：1994-01-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Ohsawa, Takashi, c/o Intellectual Property Div. ,  Fujii, Shuso, c/o Intellectual Property Div.

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C29/08 ,  G11C29/24 ,  G11C29/34 ,  G11C29/40 ,  G11C29/44

Abstract: Disclosed is a semiconductor memory with a built-in parallel bit test mode, which has a special test mode for pre-die sort that can output redundancy data and perform a parallel test on a plurality of bits for each cell array. The semiconductor memory comprises a memory circuit including memory cell arrays (11) formed on a semiconductor chip area and laid out as a plurality of blocks, the memory circuit having a redundancy function for allowing each memory cell array to be saved independently by spare rows (112) or spare columns (113), a first test circuit, provided in the memory circuit, for writing the same data to a plurality of bits of memory cells in the memory circuit and simultaneously reading the data from the plurality of bits to determine whether or not each piece of the simultaneously read data matches with each other to thereby perform a parallel test on a plurality of bits in a first parallel bit test mode specified when the semiconductor chip area is sealed in a package or is in a wafer state, and a second test circuit, provided in the memory circuit, for performing a parallel test on a plurality of bits of memory cells in the memory circuit with a degree of reduction of bits, less than a reduced number of bits of data read in the first parallel bit test mode, in a second parallel bit test mode specified when the semiconductor chip area is in a wafer state. Those bits reduced in the second parallel bit test mode are included in a unit of redundancy replacement.

公开(公告)号：EP0615251A2

公开(公告)日：1994-09-14

申请号：EP94100019.2

申请日：1994-01-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Ohsawa, Takashi, c/o Intellectual Property Div. ,  Fujii, Shuso, c/o Intellectual Property Div.

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C29/08 ,  G11C29/24 ,  G11C29/34 ,  G11C29/40 ,  G11C29/44

Abstract: Disclosed is a semiconductor memory with a built-in parallel bit test mode, which has a special test mode for pre-die sort that can output redundancy data and perform a parallel test on a plurality of bits for each cell array. The semiconductor memory comprises a memory circuit including memory cell arrays (11) formed on a semiconductor chip area and laid out as a plurality of blocks, the memory circuit having a redundancy function for allowing each memory cell array to be saved independently by spare rows (112) or spare columns (113), a first test circuit, provided in the memory circuit, for writing the same data to a plurality of bits of memory cells in the memory circuit and simultaneously reading the data from the plurality of bits to determine whether or not each piece of the simultaneously read data matches with each other to thereby perform a parallel test on a plurality of bits in a first parallel bit test mode specified when the semiconductor chip area is sealed in a package or is in a wafer state, and a second test circuit, provided in the memory circuit, for performing a parallel test on a plurality of bits of memory cells in the memory circuit with a degree of reduction of bits, less than a reduced number of bits of data read in the first parallel bit test mode, in a second parallel bit test mode specified when the semiconductor chip area is in a wafer state. Those bits reduced in the second parallel bit test mode are included in a unit of redundancy replacement.

Abstract translation: 公开了一种具有内置并行比特测试模式的半导体存储器，其具有用于可以输出冗余数据并对每个单元阵列的多个比特执行并行测试的用于管芯前分类的特殊测试模式。 半导体存储器包括存储器电路，该存储器电路包括形成在半导体芯片区域上的存储器单元阵列（11）并且被布置为多个块，存储器电路具有用于允许每个存储器单元阵列被备用行独立地保存的冗余功能（ 112）或备用列（113）;第一测试电路，设置在存储器电路中，用于将相同数据写入存储器电路中的多个存储器单元位，并同时从多个位读取数据以确定是否 或者不同时读取的数据彼此匹配，从而在半导体芯片区域被封装在封装中或处于晶片状态时指定的第一并行位测试模式中对多个位执行并行测试，以及 设置在存储器电路中的第二测试电路，用于以比特的减少程度对存储器电路中的多个存储器单元的比特进行并行测试， 在半导体芯片区域处于晶片状态时所指定的第二并行位测试模式中，在第一并行位测试模式中读取的数据的位数。 在第二个并行比特测试模式下减少的比特包含在冗余替换单元中。