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    CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
    1.
    发明公开
    CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS 审中-公开
    电路及方法测试几家半导体STORE

    公开(公告)号：EP2102869A1

    公开(公告)日：2009-09-23

    申请号：EP07845609.2

    申请日：2007-11-29

    申请人： Mosaid Technologies Incorporated

    发明人： PYEON, Hong Beom

    IPC分类号： G11C29/08 ,  G06F11/00 ,  G06F11/22 ,  G11C29/10

    CPC分类号： G11C29/32 ,  G11C29/003 ,  G11C29/40 ,  G11C2029/0409 ,  G11C2029/2602

    摘要： A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.

    COMPRESSION OF DATA TRACES FOR AN INTEGRATED CIRCUIT WITH MULTIPLE MEMORIES
    2.
    发明公开
    COMPRESSION OF DATA TRACES FOR AN INTEGRATED CIRCUIT WITH MULTIPLE MEMORIES 有权
    数据的压缩轨道为具有多个商店集成电路

    公开(公告)号：EP1745489A1

    公开(公告)日：2007-01-24

    申请号：EP05748092.3

    申请日：2005-05-11

    申请人： Qualcomm, Incorporated

    发明人： JOHN, Johnny K.

    IPC分类号： G11C29/00 ,  G01R31/3185

    CPC分类号： G06F11/348 ,  G01R31/3177 ,  G01R31/318505 ,  G06F11/3471 ,  G06F11/3476 ,  G11C29/40 ,  G11C29/56008 ,  G11C2029/0401

    摘要： Techniques for performing data tracing in an integrated circuit with multiple embedded memories are described. A trace module within the integrated circuit forms packets of trace data for memory accesses of the multiple memories. The trace module includes multiple data capture units (one for each memory) and a trace stream generator. Each data capture unit includes a register, a comparator, an address compressor, a data compressor, and a packetizer. The register stores an address for a prior memory access of the associated memory. The comparator compares an address for a current memory access against the address stored in the register. The address and data compressors perform address and data compression, respectively, for the current memory access. The packetizer forms a packet of trace data for the current memory access. The trace stream generator generates a stream containing trace data packets from all data capture units.

    Signature cell
    4.
    发明公开
    Signature cell 审中-公开
    Kennzeichnungszelle

    公开(公告)号：EP1463063A1

    公开(公告)日：2004-09-29

    申请号：EP04251764.9

    申请日：2004-03-26

    申请人： STMicroelectronics, Inc.

    发明人： Soundron, Agnel

    IPC分类号： G11C29/00

    CPC分类号： G11C29/40 ,  G11C17/14 ,  G11C2029/0405

    摘要： A signature structure and method of use for verifying a programmed state of a memory circuit of an integrated circuit is disclosed. The integrated circuit comprises a memory cell, a built-in-self-test cell, a compare cell and a signature cell. The signature cell includes a set of first conductive paths in a first level of conductive material and a set of second conductive paths in a second level of conductive material. The first level of conductive material is separated from the second level of conductive material by an insulating material. A contact structure is placed in a manner such that a first conductive path is in electrical contact with a second conductive path. The selection of a placement of the contact structure is such the first and second conductive paths are electrically coupled to a voltage reference source. The combination of the coupled and uncoupled first and second conductive paths provide the bit states of a reference signature word. The built-in-self-test structure provides addressing data to the memory structure and generates a resulting signature word. The resulting signature word is compared to the reference signature word to generate a status condition of the programmed state of the memory structure. The status condition is used to indicate a pass or fail test result regarding the programmed state of the memory structure.

    摘要翻译： 公开了用于验证集成电路的存储器电路的编程状态的签名结构和方法。 集成电路包括存储单元，内置自测单元，比较单元和签名单元。 签名单元包括在第一级导电材料中的一组第一导电路径和在第二级导电材料中的一组第二导电路径。 第一级导电材料通过绝缘材料与第二级导电材料分离。 接触结构被放置成使得第一导电路径与第二导电路径电接触。 接触结构的布置的选择是这样的，第一和第二导电路径电耦合到电压参考源。 耦合和非耦合的第一和第二导电路径的组合提供参考签名字的位状态。 内置自检结构提供寻址数据到存储器结构，并生成结果签名字。 将所得到的签名字与参考签名字进行比较，以生成存储器结构的编程状态的状态条件。 状态条件用于指示关于存储器结构的编程状态的通过或失败测试结果。

    Semiconductor integrated circuit with error detecting circuit
    6.
    发明授权
    Semiconductor integrated circuit with error detecting circuit 失效
    具有故障检测电路的半导体集成电路

    公开(公告)号：EP0833249B1

    公开(公告)日：2003-03-19

    申请号：EP97250288.4

    申请日：1997-09-25

    申请人： NEC CORPORATION

    发明人： Sasaki, Makoto, c/o NEC IC Microcomp. Sys., Ltd.

    IPC分类号： G06F11/10 ,  G11C29/00 ,  G01R31/3185

    CPC分类号： G06F11/1008 ,  G11C29/36 ,  G11C29/40

    摘要： An instruction code is stored to an instruction ROM (2) in advance and the instruction ROM (2) outputs an instruction code signal (105) corresponding to an address signal (104). A program counter (1) sequentially outputs and stores the address signal (104) in synchronization with a clock signal (101). An instruction register (5) temporarily stores and outputs the instruction code signal (105) in synchronization with the clock signal (101). A check code generating circuit (7) generates a check code signal (114) every cycle of the clock signal (101) in accordance with a signal outputted of the instruction register (5) and the address signal (104). Thereafter, a comparator (9) detects an error in operation of the instruction ROM (2) by comparing the check code signal (114) and a check data signal (106) corresponding to the instruction code and its address value.

    A METHOD AND A DEVICE FOR TESTING A MEMORY ARRAY IN WHICH FAULT RESPONSE IS COMPRESSED
    7.
    发明公开
    A METHOD AND A DEVICE FOR TESTING A MEMORY ARRAY IN WHICH FAULT RESPONSE IS COMPRESSED 审中-公开
    方法和设备与测试结果压缩存储器矩阵测试

    公开(公告)号：EP1116241A2

    公开(公告)日：2001-07-18

    申请号：EP00953059.3

    申请日：2000-07-17

    申请人： Koninklijke Philips Electronics N.V.

    发明人： MARINISSEN, Erik, J. ,  LOUSBERG, Guillaume, E., A. ,  WIELAGE, Paul

    IPC分类号： G11C29/00

    CPC分类号： G11C29/40 ,  G11C29/44

    摘要： A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row- and/or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.

    Semiconductor integrated circuit with error detecting circuit
    9.
    发明公开
    Semiconductor integrated circuit with error detecting circuit 失效
    Integrierte Halbleiterschaltung mit Fehlererkennungsschaltung

    公开(公告)号：EP0833249A1

    公开(公告)日：1998-04-01

    申请号：EP97250288.4

    申请日：1997-09-25

    申请人： NEC CORPORATION

    发明人： Sasaki, Makoto, c/o NEC IC Microcomp. Sys., Ltd.

    IPC分类号： G06F11/10 ,  G11C29/00 ,  G01R31/3185

    CPC分类号： G06F11/1008 ,  G11C29/36 ,  G11C29/40

    摘要： An instruction code is stored to an instruction ROM (2) in advance and the instruction ROM (2) outputs an instruction code signal (105) corresponding to an address signal (104). A program counter (1) sequentially outputs and stores the address signal (104) in synchronization with a clock signal (101). An instruction register (5) temporarily stores and outputs the instruction code signal (105) in synchronization with the clock signal (101). A check code generating circuit (7) generates a check code signal (114) every cycle of the clock signal (101) in accordance with a signal outputted of the instruction register (5) and the address signal (104). Thereafter, a comparator (9) detects an error in operation of the instruction ROM (2) by comparing the check code signal (114) and a check data signal (106) corresponding to the instruction code and its address value.

    摘要翻译： 指令代码预先存储在指令ROM（2）中，指令ROM（2）输出对应于地址信号（104）的指令代码信号（105）。 程序计数器（1）与时钟信号（101）同步地顺序输出并存储地址信号（104）。 指令寄存器（5）与时钟信号（101）同步地临时存储并输出指令代码信号（105）。 校验码产生电路（7）根据从指令寄存器（5）和地址信号（104）输出的信号，每周期的时钟信号（101）生成校验码信号（114）。 此后，比较器（9）通过比较校验码信号（114）和对应于指令代码及其地址值的校验数据信号（106）来检测指令ROM（2）的操作中的错误。