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    Semiconductor integrated circuit with gate-array arrangement
    2.
    发明公开
    Semiconductor integrated circuit with gate-array arrangement 失效
    Integrierte Halbleiterschaltung mit Gattermatrixstruktur。

    公开(公告)号：EP0119059A2

    公开(公告)日：1984-09-19

    申请号：EP84301523.1

    申请日：1984-03-07

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Hara, Hisashi

    IPC分类号： H01L27/02

    CPC分类号： H03K19/09441 ,  H01L23/528 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a CMOS gate-array type IC device a plurality of cell arrays in which a plurality of fundamental cells (C1, C2, ...) each having a CMOS structure are disposed in a column direction (Y) are disposed along a row direction (X) on a semiconductive substrate (32). An arbitary fundamental cell array is in direct contact with another cell array adjacent thereto along the row direction (X). One macrocell serving as a unit logical circuit component may be formed by suitably wiring two fundamental cells (C1, C2) each belonging to two neighbouring cell arrays.

    摘要翻译： 在CMOS栅极阵列型IC器件中，在列方向（Y）上配置多个具有CMOS结构的基本单元（C1，C2，...）的多个单元阵列沿行方向 （X）在半导体衬底（32）上。 任意的基本单元阵列沿与行方向（X）相邻的另一个单元阵列直接接触。 可以通过适当地布线两个属于两个相邻单元阵列的基本单元（C1，C2）来形成用作单元逻辑电路组件的一个宏单元。

    Semiconductor device
    3.
    发明公开
    Semiconductor device 失效
    Halbleiteranordnung。

    公开(公告)号：EP0062894A2

    公开(公告)日：1982-10-20

    申请号：EP82102994.9

    申请日：1982-04-07

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Iizuka, Tetsuya ,  Hara, Hisashi

    IPC分类号： H01L27/02 ,  H01L27/06

    CPC分类号： G05F3/205 ,  H01L27/0222

    摘要： A semiconductor device comprising a semiconductor substrate of the first conductivity type (120), a self substrate bias generator formed in the semiconductor substrate for generating a voltage with the opposite polarity to that of an externally applied voltage and having a capacitive element (112) and a rectifier element (114,118) and a group of circuit elements supplied with a voltage generated by the self substrate bias generator, characterized in that the semiconductor substrate of the first conductivity type is supplied with a first reference potential (V DD ) selected so as to prevent minority carriers from the capacitive element and the rectifier element from entering into the semiconductor substrate; and the circuit element group is formed in a first semiconductor region (122) formed in the semiconductor substrate.

    摘要翻译： 一种半导体器件，包括第一导电类型（120）的半导体衬底，形成在半导体衬底中的用于产生与外部施加的电压具有相反极性的电压并具有电容元件（112）的自衬底偏压发生器，以及 整流元件（114,118）和一组电路元件，其被提供有由所述自衬底偏压发生器产生的电压，其特征在于，所述第一导电类型的所述半导体衬底被提供有第一参考电位（VDD） 以防止电容元件和整流元件的少数载流子进入半导体衬底; 并且电路元件组形成在形成在半导体衬底中的第一半导体区域（122）中。

    Semiconductor integrated circuit with gate-array arrangement
    5.
    发明公开
    Semiconductor integrated circuit with gate-array arrangement 失效
    具有栅格阵列布置的半导体集成电路

    公开(公告)号：EP0119059A3

    公开(公告)日：1986-01-02

    申请号：EP84301523

    申请日：1984-03-07

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Hara, Hisashi

    IPC分类号： H01L27/02

    CPC分类号： H03K19/09441 ,  H01L23/528 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a CMOS gate-array type IC device a plurality of cell arrays in which a plurality of fundamental cells (C1, C2, ...) each having a CMOS structure are disposed in a column direction (Y) are disposed along a row direction (X) on a semiconductive substrate (32). An arbitary fundamental cell array is in direct contact with another cell array adjacent thereto along the row direction (X). One macrocell serving as a unit logical circuit component may be formed by suitably wiring two fundamental cells (C1, C2) each belonging to two neighbouring cell arrays.