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    CELLULE LOGIQUE RECONFIGURABLE A BASE DE TRANSISTORS MOSFET DOUBLE GRILLE
    1.
    发明公开
    CELLULE LOGIQUE RECONFIGURABLE A BASE DE TRANSISTORS MOSFET DOUBLE GRILLE 有权
    可重构逻辑单元与双门MOSFET晶体管

    公开(公告)号：EP2171851A2

    公开(公告)日：2010-04-07

    申请号：EP08826630.9

    申请日：2008-07-11

    申请人： Ecole Centrale de Lyon ,  Centre National de la Recherche Scientifique (CNRS)

    发明人： O'CONNOR, Ian D. ,  HASSOUNE, Ilham

    IPC分类号： H03K19/08 ,  H03K19/0944 ,  H03K19/173

    CPC分类号： H03K19/09441 ,  H03K19/0813 ,  H03K19/1738

    摘要： The invention relates to reconfigurable logic cells made up of double-gate MOSFET transistors (DG MOSFET) comprising n inputs (A,B), n being greater than or equal to 2, which can carry out at least four logical functions permitting the processing of the logical signals provided at the n inputs (A,B). According to the invention, the cell comprises at least one first branch between the earth and the cell output (F) with n MOSFET transistors (M1,M2) of the N type with a double gate in series and n-1 branches in parallel with the first branch, each provided with a MOSFET transistor (M3) of the N type with a double gate, each of the logical functions corresponding to a given configuration of the cell where a specific set of control signals (C1,C2) is applied to the back gate of at least some of the transistors (M2,M3), each control signal (C1,C2) placing the transistor (M2,M3) in a particular operating mode, the n inputs (A,B) being each connected to the front gate of one of the n transistors (M1,M2) of the first branch, n-1 inputs (B) also being connected to the front gate of one (M3) of the n-1 transistors of the n-1 branches parallel to the first branch.

    CURRENT-DRIVEN ENFET LOGIC CIRCUITS
    3.
    发明授权
    CURRENT-DRIVEN ENFET LOGIC CIRCUITS 失效
    电流驱动ENFET逻辑电路

    公开(公告)号：EP0110916B1

    公开(公告)日：1990-10-03

    申请号：EP83901688.8

    申请日：1983-05-03

    申请人： Hughes Aircraft Company

    发明人： HICKLING, Ronald M. ,  LANDENBERGER, Jay E.

    IPC分类号： H03K19/094

    CPC分类号： H03K19/09441 ,  H03K19/0952

    摘要： An enhancement-mode field effect transistor (ENFET) logic circuit providing greater fan-out capability. The logic circuit employs a conventional common-source inverter section (19), but additionally incorporates a current-driving section (25) which drives the common-source inverter section. A current-driven inverter logic circuit is realized by employing a second ENFET transistor (23) to drive the gate of the common-source inverter section (19). A current-driven (NOR) gate is realized by employing to ENFET transistors in parallel which drive the common-source inverter section. Also a current-driven NAND gate is realized by utilizing a single transistor having two gate inputs to drive the common-source inverter section. The use of sweep-out circuitry allows for control of the operational speed of the device. The logic circuit designes have high fanout capability compared to the common-source inverter circuit alone.

    Semiconductor device comprising insulated gate field effect transistors
    5.
    发明公开
    Semiconductor device comprising insulated gate field effect transistors 失效
    具有绝缘栅型场效应晶体管的半导体器件。

    公开(公告)号：EP0158401A1

    公开(公告)日：1985-10-16

    申请号：EP85200504.0

    申请日：1985-04-01

    申请人： Philips Electronics N.V.

    发明人： Wagenaar, Kornelis Jan c/o INT. OCTROOIBUREAU B.V.

    IPC分类号： H01L27/02 ,  H03K19/094

    CPC分类号： H03K19/09441 ,  H01L27/0218

    摘要： A semiconductor device comprising insulated gate field effect transistors, with which logic gate circuits having a satisfactory switching speed and a high packing density can be realized. The logic gate circuits are composed of transistor structures having a common source zone (22), which each comprise a gate (33), a second semiconductor zone (25) and one or more drain zones (28) and are manufactured in DMOS technology. The dates (33) are strip-shaped or have at least a strip-shaped part. The gate circuits can be integrated in a simple manner with one or more high-voltage transistors manufactured in DMOS technology.

    Resistive gate field effect transistor logic family
    6.
    发明公开
    Resistive gate field effect transistor logic family 失效
    逻辑家庭及Widerstandstor场效应晶体管。

    公开(公告)号：EP0137257A2

    公开(公告)日：1985-04-17

    申请号：EP84110056.3

    申请日：1984-08-23

    申请人： International Business Machines Corporation

    发明人： Bertin, Claude Louis

    IPC分类号： H01L29/62 ,  H03K19/094

    CPC分类号： H01L29/435 ,  H03K19/09441

    摘要： @ A family of digital logic circuits constructed with resistive gate field effect transistors is provided. The logic circuits are comprised of AND and OR circuits, each implemented with resistive gate devices. In constructing an AND circuit (Figure 1 the resistive gate (6) lies along the length of the channel region between the source (2) and drain (4) of the device. Logic input signals (at 10, 12, 13) are selectively applied along the length of the channel region to the resistive gate. The device will conduct between source and drain only if all points along the channel are above the local threshold voltage of the channel region which will occur when appropriate logic signals are applied simultaneously to all logic input terminals. A logic OR device (Figure 6) is realized when the resistive gate (45) is formed transverse to the channel such that each input to the gate controls a portion of the channel between the source (44) and drain (42). NAND and NOR circuits are provided using the resistive gate logic device in an inverting circuit context.

    SCAN SIGNAL LINE DRIVER CIRCUIT AND DISPLAY APPARATUS HAVING SAME
    8.
    发明公开
    SCAN SIGNAL LINE DRIVER CIRCUIT AND DISPLAY APPARATUS HAVING SAME 审中-公开
    AN IT IT IT IT IT IT IT IT IT IT IT IT IT IT

    公开(公告)号：EP2515290A1

    公开(公告)日：2012-10-24

    申请号：EP10837346.5

    申请日：2010-10-14

    申请人： Sharp Kabushiki Kaisha

    发明人： TAKAHASHI, Yoshihisa ,  IWASE, Yasuaki

    IPC分类号： G09G3/36 ,  G02F1/133 ,  G09G3/20 ,  H03K19/0175

    CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/28 ,  H03K19/01728 ,  H03K19/09441

    摘要： It is an object to realize a gate driver that can cause a scanning signal to quickly fall after a charge period in each row ends.
    A gate driver is configured by two shift registers. In an n-th stage bistable circuit (SR(n)) in an entire shift register (410), a region netA connected to a gate terminal of a thin-film transistor that increases a potential of an output node for outputting a state signal (Q) based on a first clock (CKA) is set to an on level based on the state signal (Q) outputted from an (n-2)-th stage bistable circuit (SR(n-2), the region netA is set to an off level based on the state signal (Q) outputted from an (n+2)-th stage bistable circuit (SR(n+2)), and the output node is set to an off level based on the state signal (Q) outputted from an (n+3)-th stage bistable circuit (SR(n+3)).

    摘要翻译： 其目的是实现一个栅极驱动器，其可以在每行的充电周期结束后使扫描信号快速下降。 门驱动器由两个移位寄存器配置。 在整个移位寄存器（410）中的第n级双稳态电路（SR（n））中，连接到薄膜晶体管的栅极端子的区域netA，其增加用于输出状态信号的输出节点的电位 基于从第（n-2）级双稳态电路（SR（n-2））输出的状态信号（Q），基于第一时钟（CKA）的区域netA被设置为导通电平 基于从第（n + 2）级双稳态电路（SR（n + 2））输出的状态信号（Q）设置为关闭电平，并且基于状态信号将输出节点设置为关闭电平 （n + 3）级双稳态电路（SR（n + 3））输出的输出信号（Q）。

    Logic gate, scan driver and organic light emitting diode display using the same
    9.
    发明公开
    Logic gate, scan driver and organic light emitting diode display using the same 有权
    Logik-Gate，Zeilentreiber und organische lichtemittierende Diodenanzeige damit

    公开(公告)号：EP1912332A2

    公开(公告)日：2008-04-16

    申请号：EP07114023.0

    申请日：2007-08-08

    申请人： Samsung SDI Co., Ltd.

    发明人： Chung, Bo-yong Legal & IP Team, Samsung SDI Co., LTD. ,  Lee, Wang-jo, Legal & IP Team, Samsung SDI Co., LTD. ,  Kim, Hyung-soo, Legal & IP Team, Samsung SDI Co., LTD. ,  Choi, Sang-moo, Legal & IP Team, Samsung SDI Co., LTD.

    IPC分类号： H03K19/0944 ,  G09G3/32

    CPC分类号： H03K19/09441 ,  G09G3/3266 ,  G09G2310/06

    摘要： Disclosed is a logic gate and a scan driver capable of being realized with MOS transistors of a single polarity type only, preferably PMOS transistors. The logic gate comprises a plurality of input terminals (IN1-IN3), a first driver (10), a second driver (12), a third driver (14), a control transistors (M8), a first capacitor (C2), and a fourth driver (16). The first driver (12) is adapted to provide a first power supply voltage (VDD) to a first node (N1) corresponding to a logic combination of the plurality of input signals and the second driver (14) is adapted to provide a second power supply voltage (VSS) to the first node (N1) when the first driver (12) does not provide the first power supply voltage (VDD) to the first node (N1). The third driver (14) is adapted to provide the first power supply voltage (VDD) to an output terminal of the logic gate when the second power supply voltage (VSS) is provided to the first node (N1) and the fourth driver (16) is adapted to provide the second power supply voltage (VSS) to the gate electrode of the control transistor (M8) when the third driver (14) does not provide the first power supply voltage (VDD) to the output terminal. Each of the first driver (10), the second driver (12), the third driver (14), and the fourth driver (16) comprises at least one transistor. These transistors and the control transistor are MOS transistors of the same polarity type.

    摘要翻译： 公开了一种逻辑门和扫描驱动器，其能够仅用单极性类型的MOS晶体管实现，优选为PMOS晶体管。 逻辑门包括多个输入端（IN1-IN3），第一驱动器（10），第二驱动器（12），第三驱动器（14），控制晶体管（M8），第一电容器（C2） 和第四驱动器（16）。 第一驱动器（12）适于向与多个输入信号的逻辑组合相对应的第一节点（N1）提供第一电源电压（VDD），并且第二驱动器（14）适于提供第二功率 当第一驱动器（12）不向第一节点（N1）提供第一电源电压（VDD）时，向第一节点（N1）提供电源电压（VSS）。 当向第一节点（N1）和第四驱动器（16）提供第二电源电压（VSS）时，第三驱动器（14）适于向逻辑门的输出端提供第一电源电压（VDD） ）适于当第三驱动器（14）不向输出端子提供第一电源电压（VDD）时，向控制晶体管（M8）的栅电极提供第二电源电压（VSS）。 第一驱动器（10），第二驱动器（12），第三驱动器（14）和第四驱动器（16）中的每一个包括至少一个晶体管。 这些晶体管和控制晶体管是相同极性类型的MOS晶体管。