公开(公告)号：EP0499985B1

公开(公告)日：1999-06-02

申请号：EP92102522.7

申请日：1992-02-14

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

发明人： Saeki, Yukihiro, c/o Intellectual Property Div. ,  Matsumoto, Osamu, c/o Intellectual Property Div. ,  Yoshida, Masayuki, c/o Intellectual Property Div. ,  Mizutani, Takahide, c/o Intellectual Property Div. ,  Chida, Nobuyoshi, c/o Intellectual Property Div. ,  Shigematsu, Tomohisa, c/o Intellectual Prop. Div. ,  Uemura, Teruo, c/o Intellectual Property Div. ,  Toyoda, Kenji, c/o Intellectual Property Div. ,  Takamura, Hiroyuki, c/o Intellectual Property Div.

IPC分类号： H01L21/336 ,  H01L21/82

CPC分类号： H01L27/11521 ,  Y10S148/106

公开(公告)号：EP0499985A3

公开(公告)日：1992-09-16

申请号：EP92102522.7

申请日：1992-02-14

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

发明人： Saeki, Yukihiro, c/o Intellectual Property Div. ,  Matsumoto, Osamu, c/o Intellectual Property Div. ,  Yoshida, Masayuki, c/o Intellectual Property Div. ,  Mizutani, Takahide, c/o Intellectual Property Div. ,  Chida, Nobuyoshi, c/o Intellectual Property Div. ,  Shigematsu, Tomohisa, c/o Intellectual Prop. Div. ,  Uemura, Teruo, c/o Intellectual Property Div. ,  Toyoda, Kenji, c/o Intellectual Property Div. ,  Takamura, Hiroyuki, c/o Intellectual Property Div.

IPC分类号： H01L21/336 ,  H01L21/82

CPC分类号： H01L27/11521 ,  Y10S148/106

摘要： A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film (22) and a gate oxide film (21) on a semiconductor substrate (20), depositing a first conductive layer (23) on an entire surface of the resultant structure, selectively etching the first conductive layer (23) located in a region other than an element region, oxidation of the entire surface of the resultant structure, depositing a second conductive layer (27) on an entire surface of the resultant structure, and etching the first conductive layer (23), the oxide film (26), and the second conductive layer (27) using the same mask to form a plurality of floating gates by the first conductive layer (23) and to form a plurality of control gates by the second conductive layer (27), wherein the step of selectively etching the first conductive layer (23) includes the first etching step of forming cell slits (24) for separating the plurality of floating gates from each other and the second etching step of forming removed regions (25) each of which includes only one end of each of the plurality of control gates.

公开(公告)号：EP0499985A2

公开(公告)日：1992-08-26

申请号：EP92102522.7

申请日：1992-02-14

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

发明人： Saeki, Yukihiro, c/o Intellectual Property Div. ,  Matsumoto, Osamu, c/o Intellectual Property Div. ,  Yoshida, Masayuki, c/o Intellectual Property Div. ,  Mizutani, Takahide, c/o Intellectual Property Div. ,  Chida, Nobuyoshi, c/o Intellectual Property Div. ,  Shigematsu, Tomohisa, c/o Intellectual Prop. Div. ,  Uemura, Teruo, c/o Intellectual Property Div. ,  Toyoda, Kenji, c/o Intellectual Property Div. ,  Takamura, Hiroyuki, c/o Intellectual Property Div.

IPC分类号： H01L21/336 ,  H01L21/82

CPC分类号： H01L27/11521 ,  Y10S148/106

摘要： A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film (22) and a gate oxide film (21) on a semiconductor substrate (20), depositing a first conductive layer (23) on an entire surface of the resultant structure, selectively etching the first conductive layer (23) located in a region other than an element region, oxidation of the entire surface of the resultant structure, depositing a second conductive layer (27) on an entire surface of the resultant structure, and etching the first conductive layer (23), the oxide film (26), and the second conductive layer (27) using the same mask to form a plurality of floating gates by the first conductive layer (23) and to form a plurality of control gates by the second conductive layer (27), wherein the step of selectively etching the first conductive layer (23) includes the first etching step of forming cell slits (24) for separating the plurality of floating gates from each other and the second etching step of forming removed regions (25) each of which includes only one end of each of the plurality of control gates.

摘要翻译： 半导体存储器件的制造方法包括以下步骤：在半导体衬底（20）上选择性地形成场氧化物膜（22）和栅氧化膜（21），在第一导电层（23）的整个表面上沉积第一导电层 所得到的结构，选择性地蚀刻位于元件区域以外的区域的第一导电层（23），所得结构的整个表面的氧化，在所得结构的整个表面上沉积第二导电层（27） 并使用相同的掩模蚀刻第一导电层（23），氧化膜（26）和第二导电层（27），以由第一导电层（23）形成多个浮栅，并形成多个 通过第二导电层（27）的控制栅极，其中选择性蚀刻第一导电层（23）的步骤包括形成用于将多个浮置栅极彼此分离的单元狭缝（24）的第一蚀刻步骤 形成除去区域（25）的第二蚀刻步骤，每个蚀刻步骤仅包括多个控制栅极中的每一个的一端。