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1.发明授权
公开(公告)号：EP2926260B1
公开(公告)日：2019-04-03
申请号：EP14740574.0
申请日：2014-01-17
申请人： Kandou Labs S.A.
发明人： HOLDEN, Brian , FOX, John , HUNT, Peter , KEAY, John , SHOKROLLAHI, Amin , SIMPSON, Richard , SINGH, Anant , STEWART, Andrew , SURACE, Giuseppe
IPC分类号： H04L25/02 , H04L25/493 , G06F13/00 , H03M5/16
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公开(公告)号：EP2979388B1
公开(公告)日：2020-02-12
申请号：EP14785898.9
申请日：2014-04-15
申请人： Kandou Labs, S.A.
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公开(公告)号：EP2979388A1
公开(公告)日：2016-02-03
申请号：EP14785898.9
申请日：2014-04-15
申请人： Kandou Labs S.A.
发明人： HOLDEN, Brian , FOX, John , HORMATI, Ali , HUNT, Peter , KEAY, John , SHOKROLLAHI, Amin , SIMPSON, Richard , SINGH, Anant , STEWART, Andrew , SURACE, Giuseppe , ULRICH, Roger
摘要： Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.
摘要翻译： 描述了用于通过物理信道传输数据的系统和方法，以在发射设备和以低功率利用率高速运行的接收设备之间提供高带宽，低等待时间接口。 通过使用矢量信令代码在四线组上使用组信号执行通信，其中组中的每个线都携带可以采用四个信号值中的一个的低摆动信号。 用于组信令通信的优选特性公开了导线组的拓扑和设计。
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4.发明公开METHODS AND SYSTEMS FOR CHIP-TO-CHIP COMMUNICATION WITH REDUCED SIMULTANEOUS SWITCHING NOISE 审中-公开方法和系统具有减少干扰的同时开关芯片到芯片通信
公开(公告)号：EP2926260A1
公开(公告)日：2015-10-07
申请号：EP14740574.0
申请日：2014-01-17
申请人： Kandou Labs S.A.
发明人： HOLDEN, Brian , FOX, John , HUNT, Peter , KEAY, John , SHOKROLLAHI, Amin , SIMPSON, Richard , SINGH, Anant , STEWART, Andrew , SURACE, Giuseppe
CPC分类号： H04L25/4906 , G06F13/426 , H03M5/16 , H03M5/20 , H04L25/0272 , H04L25/4917 , H04L25/493 , H04L69/04 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.
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