利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

43 条记录 (耗时 0.016 秒)

    ADAPTIVE VOLTAGE SCALING OF RECEIVER
    3.
    发明公开
    ADAPTIVE VOLTAGE SCALING OF RECEIVER 审中-实审

    公开(公告)号：EP4372397A3

    公开(公告)日：2024-08-21

    申请号：EP24167938.0

    申请日：2018-12-12

    申请人： Kandou Labs S.A.

    发明人： TAJALLI, Armin

    IPC分类号： G01R31/30 ,  G05F1/10 ,  G06F1/26 ,  G05F1/46 ,  G06F1/324 ,  G06F1/3296

    CPC分类号： G01R31/3004 ,  G01R31/3016 ,  G06F1/3296 ,  G05F1/462 ,  G06F1/324 ,  Y02D10/00

    摘要： Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

    ADAPTIVE VOLTAGE SCALING OF RECEIVER
    4.
    发明公开
    ADAPTIVE VOLTAGE SCALING OF RECEIVER 审中-实审

    公开(公告)号：EP4372397A2

    公开(公告)日：2024-05-22

    申请号：EP24167938.0

    申请日：2018-12-12

    申请人： Kandou Labs S.A.

    发明人： TAJALLI, Armin

    IPC分类号： G01R31/30

    CPC分类号： G01R31/3004 ,  G01R31/3016 ,  G06F1/3296 ,  G05F1/462 ,  G06F1/324 ,  Y02D10/00

    摘要： Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

    HIGH PERFORMANCE PHASE LOCKED LOOP
    5.
    发明公开
    HIGH PERFORMANCE PHASE LOCKED LOOP 审中-公开

    公开(公告)号：EP3826184A1

    公开(公告)日：2021-05-26

    申请号：EP20217623.6

    申请日：2017-04-21

    申请人： Kandou Labs, S.A.

    发明人： TAJALLI, Armin

    IPC分类号： H03L7/06 ,  H03L7/00 ,  H03L7/07 ,  H03L7/087 ,  H03L7/091

    摘要： Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.