公开(公告)号：EP1776764A2

公开(公告)日：2007-04-25

申请号：EP05773567.2

申请日：2005-07-27

申请人： Koninklijke Philips Electronics N.V.

发明人： DEKATE, Prashant ,  LEENAERTS, Dominicus, M., W.

IPC分类号： H03K23/50 ,  H03K23/54

CPC分类号： H03K23/505 ,  H03K23/662

摘要： A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The circuit further comprises an end of count circuit (20) coupled to the binary counter and generating an End Of Count signal (EOC) for a clock (Ck) period after every even integer number periods of the clock signal (Ck), the end of count signal (EOC) being inputted to an input (IN) of the counter (10). The circuit further includes an output generator (30) coupled to the binary counter and to the clock signal (Ck), the output generator (30) generating an output signal (OUT) having a frequency which is substantially equal with the frequency of the frequency signal (Ck) divided by the odd division factor.

摘要翻译： 提供奇数整数除法因子的分频器包括提供偶数整数除法因数的二进制计数器，该偶数整数除法因数是小于奇数除法因数的第一偶数，二进制计数器具有用于接收周期性时钟信号的时钟输入（ Ck）具有频率。 该电路还包括耦合到二进制计数器的计数结束电路（20），并且在时钟信号（Ck）的每个偶数整数周期之后的时钟（Ck）周期内产生计数结束信号（EOC），结束 的计数信号（EOC）被输入到计数器（10）的输入（IN）。 该电路还包括耦合到二进制计数器和时钟信号（Ck）的输出发生器（30），输出发生器（30）产生具有与频率的频率基本相等的频率的输出信号（OUT） 信号（Ck）除以奇数分频因子。