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1.发明公开FIFO BUFFER THAT CAN READ AND/OR WRITE A SELECTABLE NUMBER OF DATA WORDS PER BUS CYCLE 审中-公开FIFO缓冲液中数据字每个总线周期读取和/或可能书面数量可选
公开(公告)号：EP1402339A1
公开(公告)日：2004-03-31
申请号：EP02733128.9
申请日：2002-06-03
发明人： EHMANN, Gregory, E.
IPC分类号： G06F5/06
CPC分类号： G06F5/10
摘要： A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a memory array. In addition, the multiple transfers are performed during one bus cycle and the number of transfers may be selectable. FIFO control circuitry limits the number of data elements transferred in response to the state of the memory array including almost empty or almost full.
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公开(公告)号：EP1634089A1
公开(公告)日：2006-03-15
申请号：EP04735277.8
申请日：2004-05-28
IPC分类号： G01R31/3185
CPC分类号： G01R31/31858 , G01R31/31937
摘要： A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (300), a target circuit (332) having logic circuitry that processes data in response to an operational clock signal (308) having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock (309) having several clock-state transitions that occur during at least one clock period of the operational clock (308). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers (340) that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.
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公开(公告)号：EP1397748A2
公开(公告)日：2004-03-17
申请号：EP02735695.5
申请日：2002-05-29
CPC分类号： H04L7/0008 , H04L25/14
摘要： In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.
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4.发明公开PARALLEL DATA COMMUNICATION HAVING SKEW INTOLERANT DATA GROUPS AND DATA VALIDITY INDICATOR 审中-公开并行数据与SKEW不耐数据组和验证数据中的指标会议
公开(公告)号：EP1433293A1
公开(公告)日：2004-06-30
申请号：EP02767791.3
申请日：2002-09-16
CPC分类号： H04L7/0008 , H04L25/14
摘要： A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.
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公开(公告)号：EP1421496A2
公开(公告)日：2004-05-26
申请号：EP02755557.2
申请日：2002-08-21
发明人： EHMANN, Gregory, E. , SAXENA, Swati
IPC分类号： G06F11/34
CPC分类号： G06F11/349 , G06F2201/86
摘要： An adaptive data communication approach permits communication bus monitoring by using a reconfigurable bus monitor built into the CPU bus structure and adapted to report back to the CPU in response to detecting certain CPU-programmed events. In one particular example embodiment, a circuit arrangement having a CPU circuit communicates with another device over a communication channel while a reconfigurable circuit monitors the communication channel. The CPU circuit configures the reconfigurable circuit for monitoring any of various types of event expected to occur on the communication channel. The reconfigurable circuit collects signals passed on the communication channel and reports back to the CPU circuit when data indicative of the first event type occurs on the communication channel. In response to the data indicative of the monitored event, the CPU circuit reconfigures the reconfigurable circuit to monitor for another event type occurring on the communication channel and thereby permits for an adaptive evaluation of the communication channel. Another aspect of the invention is directed to the CPU redirecting data communication in response to this adaptive evaluation.
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公开(公告)号：EP1397895A2
公开(公告)日：2004-03-17
申请号：EP02733052.1
申请日：2002-05-28
发明人： EHMANN, Gregory, E.
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/04 , H04L25/4908
摘要： A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.
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