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公开(公告)号：EP1982205B1
公开(公告)日：2010-12-22
申请号：EP07700042.0
申请日：2007-01-04
申请人： NXP B.V.
发明人： WAAYERS, Tom , MEIRLEVEDE, Johan, C. , PRICE, David, P. , SCHOMANN, Norbert , SOLBACH, Ruediger , FLEURY, Herve , POELS, Jozef, R.
IPC分类号： G01R31/3185
CPC分类号： G01R31/31858
摘要： A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK). Clocking hardware is also provided, and these provide at-speed testing which enables on the fly switching between a relatively slow tester driven clock for the shift modes and faster clocks generated by on-chip PLLs and divider circuits for the test mode.
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公开(公告)号：EP2151051A1
公开(公告)日：2010-02-10
申请号：EP08748273.3
申请日：2008-05-07
申请人： ATI Technologies ULC
发明人： AHMADI, Rubil
CPC分类号： G01R31/31858 , G01R31/318536
摘要： A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.
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公开(公告)号：EP1525488B1
公开(公告)日：2009-01-14
申请号：EP03727883.5
申请日：2003-06-05
IPC分类号： G01R31/3185
CPC分类号： G01R31/31701 , G01R31/31858
摘要： An electronic circuit that includes components that operate asynchronously of one another. An interface element has inputs coupled to a respective one of the components. The interface element supplies a logic output signal that is a logic function of signals at the inputs and dependent on the relative timing of the signals at the inputs. The electronic circuit is switched to a test mode, in which test input signals are applied to the electronic circuit from a test signal source. During test a difference is caused to occur between the time intervals after which the test signal source affects different ones of the signals at the inputs of the interface element. Preferably the test control circuit activates said difference in the test mode and not in the normal operating mode.
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公开(公告)号：EP1634089A1
公开(公告)日：2006-03-15
申请号：EP04735277.8
申请日：2004-05-28
IPC分类号： G01R31/3185
CPC分类号： G01R31/31858 , G01R31/31937
摘要： A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (300), a target circuit (332) having logic circuitry that processes data in response to an operational clock signal (308) having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock (309) having several clock-state transitions that occur during at least one clock period of the operational clock (308). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers (340) that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.
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公开(公告)号：EP1430320B1
公开(公告)日：2005-10-26
申请号：EP02772236.2
申请日：2002-08-30
IPC分类号： G01R31/3185
CPC分类号： G01R31/31858
摘要： The invention relates to an electronic component (1) with an integrated semiconductor circuit that comprises a core (2) with functional flip-flops. A part of the functional flip-flops is linked as input FFs (7) with input pins (3) of the component (1) and a part of the functional flip-flops is linked as output FFs (8) with output pins (6) of the component (1). In order to allow for efficient and cost-effective ASIC qualification methods that can be carried out rapidly and that take into consideration the growing complexity of integrated circuits and the rapid development of technology, the invention provides a method and a device wherein the input FFs (7) and the output FFs (8) are interconnected to a shift register during a qualification measurement of the component (1).
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公开(公告)号：EP0702241B1
公开(公告)日：2004-05-12
申请号：EP95305861.7
申请日：1995-08-22
发明人： Warren, Robert
IPC分类号： G01R31/3173 , G01R31/3185 , G06F11/24 , G06F11/267 , H03K3/037
CPC分类号： G06F11/2236 , G01R31/31858 , H03K3/0375
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公开(公告)号：EP0994361A3
公开(公告)日：2001-09-05
申请号：EP99117109.1
申请日：1999-08-28
IPC分类号： G01R31/3185 , G01R31/3193
CPC分类号： G01R31/3016 , G01R31/31858 , G01R31/31937
摘要： A new-style method of measuring the flush delay on chips in LSSD design is described. The flush delay is a measurement variable for the switching speed of a chip. First the clock inputs of all flip-flops of a scan path are activated in order to switch the flip-flops to continuity. Then a signal edge is applied to the scan input which appears with a time delay at the scan output of the flip-flop chain. From the time at which the signal edge is applied to the scan input, the scan output is scanned at periodic intervals. The measurements obtained are compared against a pre-set expected value; all measurement values deviating from the expected value are counted. The flush delay is produced by multiplying the number of deviating measurement values by the measurement period. In contrast to previous measurement methods, in the method presented here a single measurement is sufficient to determine the flush delay. It is also possible to measure the flush delays of several scan paths in parallel.
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公开(公告)号：EP0846956A2
公开(公告)日：1998-06-10
申请号：EP97203529.9
申请日：1997-11-12
发明人： Nagai, Hajime
IPC分类号： G01R31/3185
CPC分类号： G01R31/31858 , G01R31/318541
摘要： Logical device (1) comprises a combinational circuit (2) and a sequential circuit (3). The sequential circuit (3) has a holding means (5) which is between the combinational circuit (2) and flip-flops (4) of the sequential circuit (3). The output data of the holding means (5) are not changed until a control signal is applied to a control terminal (10). The performance of the combinational circuit (2) in the logical device (1) can be checked.
摘要翻译： 逻辑器件（1）包括组合电路（2）和顺序电路（3）。 顺序电路（3）具有位于顺序电路（3）的组合电路（2）和触发器（4）之间的保持装置（5）。 控制信号被施加到控制端子（10）之前，保持装置（5）的输出数据不改变。 可以检查逻辑设备（1）中组合电路（2）的性能。
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公开(公告)号：EP0394611B1
公开(公告)日：1995-07-26
申请号：EP90100791.4
申请日：1990-01-16
IPC分类号： G06F11/26 , G01R31/318
CPC分类号： G01R31/318552 , G01R31/31858
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10.发明公开Built-in test circuitry providing simple and accurate AC test of digital microcircuits with low bandwidth test equipment and probe stations 失效内置测试电路提供简单和准确的低带测试设备和探测站数字微处理器的交流测试
公开(公告)号：EP0545286A3
公开(公告)日：1993-07-14
申请号：EP92120180.2
申请日：1992-11-26
发明人： Farwell, William D.
IPC分类号： G01R31/318 , G06F11/26
CPC分类号： G01R31/30 , G01R31/318552 , G01R31/31858
摘要： Circuitry and techniques are disclosed for transferring data between the automatic test equipment (ATE) and an integrated circuit under test pursuant to a slow clock that can have an arbitrarily long period, and for operating storage elements in the integrated circuit pursuant to a fast clock having a short period that corresponds to the clock rate at which combinatorial networks in the integrated circuit are to be tested. In one embodiment, input latches at inputs of the integrated circuit receive test data from the ATE, and output latches at the outputs provide test result data for the ATE. Pursuant the alternating single cycles of the slow clock and the fast clock, the delays through combinatorial networks between of a data propagation path between an input latch and an output latch are tested pursuant to the fast clock. In another embodiment, test data is serially scanned into scan registers pursuant to a series of slow clock cycles. After the test data has been scanned in, the scan registers are operated parallel to test the delays of Combinatorial networks between the scan registers.
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