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    SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES
    3.
    发明公开
    SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES 有权
    可扩展的结构对于逻辑器件可编程高密度和ZWEIEBENIGEN分层连接资源

    公开(公告)号：EP1188241A1

    公开(公告)日：2002-03-20

    申请号：EP00941247.9

    申请日：2000-06-06

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： AGRAWAL, Om, P. ,  STANLEY, Claudia, A. ,  HE, Xiaojie (Warren) ,  METZGER, Larry, R. ,  SIMON, Robert, A. ,  ILGENSTEIN, Kerry, A.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1778

    摘要： An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100 % intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.