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    Improved programmable logic device
    3.
    发明公开
    Improved programmable logic device 失效
    所述可编程逻辑器件。

    公开(公告)号：EP0196771A2

    公开(公告)日：1986-10-08

    申请号：EP86301336.3

    申请日：1986-02-25

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： Turner, John E. ,  Rutledge, David L.

    IPC分类号： H03K19/177 ,  G06F11/26

    CPC分类号： H03K19/1736 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

    摘要： An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. The PLD includes a serial register latch (SRL) 30 which is coupled to the product terms of the PLD array 10. Input programming data for a selected row of the array is serially entered into the SRL 1 0, and during a programming cycle the SRL data is employed to simultaneously program the storage elements of the selected row to either the enhancement mode or the depletion mode. The data programmed into the array 10 may be verified at high speed. The status of each of the cells in the selected row can be sensed using the normal sense amplifiers and loaded into the SRL 30 in parallel, and thereafter serially shifted out of the PLD for external verification. The PLD output logic and sense amplifiers can be functionally validated independent of the data in the array. Test data such as apparent array patterns are serially loaded into the SRL, and thereafter forced onto the normal sense amplifier inputs, propagated through the output logic and read out of the device output pin.

    Improved programmable logic device
    4.
    发明公开
    Improved programmable logic device 失效
    改进的可编程逻辑器件

    公开(公告)号：EP0523817A3

    公开(公告)日：1994-03-16

    申请号：EP92202930.1

    申请日：1986-02-25

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： Turner, John E. ,  Rutledge, David L.

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/1736 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

    摘要： A programmable logic device comprises a plurality of input lines (103-105), a plurality of product terms (111,113) and an array of programmable cells at the intersections of the input lines and product terms. Sensing amplifiers (112,114) are coupled respectively to the product terms and provide logical sense signals. These are applied through a shift register latch (112,122) to output logic macro-circuits (124,138) each of which receives the logical sense signals associated with eight product terms. The output logic macro-circuits can perform predetermined logical functions on at least selected ones of the logical sense signals, and provide outputs to device terminals dependent thereon.

    摘要翻译： 可编程逻辑器件包括多个输入线（103-105），多个乘积项（111,113）以及在输入线和乘积项的交点处的可编程单元阵列。 感测放大器（112,114）分别耦合到产品项并提供逻辑感测信号。 这些通过移位寄存器锁存器（112,122）被施加到输出逻辑宏电路（124,138），每个逻辑宏电路接收与八个乘积项相关联的逻辑感测信号。 输出逻辑宏电路可以对逻辑感测信号中的至少选定逻辑感测信号执行预定的逻辑功能，并且向依赖于其的设备端子提供输出。

    Improved programmable logic device
    5.
    发明公开
    Improved programmable logic device 失效
    Programmierbare logische Schaltung。

    公开(公告)号：EP0523817A2

    公开(公告)日：1993-01-20

    申请号：EP92202930.1

    申请日：1986-02-25

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： Turner, John E. ,  Rutledge, David L.

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/1736 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

    摘要： A programmable logic device comprises a plurality of input lines (103-105), a plurality of product terms (111,113) and an array of programmable cells at the intersections of the input lines and product terms. Sensing amplifiers (112,114) are coupled respectively to the product terms and provide logical sense signals. These are applied through a shift register latch (112,122) to output logic macro-circuits (124,138) each of which receives the logical sense signals associated with eight product terms. The output logic macro-circuits can perform predetermined logical functions on at least selected ones of the logical sense signals, and provide outputs to device terminals dependent thereon.

    摘要翻译： 可编程逻辑器件包括多个输入线（103-105），多个乘积项（111,113）和输入线与乘积项的交点处的可编程单元阵列。 感测放大器（112,114）分别耦合到产品术语并提供逻辑感测信号。 这些通过移位寄存器锁存器（112,122）施加到输出逻辑宏电路（124,138），每个逻辑宏电路接收与八个乘积项相关联的逻辑检测信号。 输出逻辑宏电路可以在至少选定的逻辑检测信号中执行预定的逻辑功能，并且向依赖于其的设备终端提供输出。

    Improved programmable logic device
    6.
    发明公开
    Improved programmable logic device 失效
    改进的可编程逻辑器件

    公开(公告)号：EP0196771A3

    公开(公告)日：1987-12-16

    申请号：EP86301336

    申请日：1986-02-25

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： Turner, John E. ,  Rutledge, David L.

    IPC分类号： H03K19/177 ,  G06F11/26

    CPC分类号： H03K19/1736 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

    摘要： An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. The PLD includes a serial register latch (SRL) 30 which is coupled to the product terms of the PLD array 10. Input programming data for a selected row of the array is serially entered into the SRL 1 0, and during a programming cycle the SRL data is employed to simultaneously program the storage elements of the selected row to either the enhancement mode or the depletion mode. The data programmed into the array 10 may be verified at high speed. The status of each of the cells in the selected row can be sensed using the normal sense amplifiers and loaded into the SRL 30 in parallel, and thereafter serially shifted out of the PLD for external verification. The PLD output logic and sense amplifiers can be functionally validated independent of the data in the array. Test data such as apparent array patterns are serially loaded into the SRL, and thereafter forced onto the normal sense amplifier inputs, propagated through the output logic and read out of the device output pin.