公开(公告)号：EP1170666A3

公开(公告)日：2002-06-26

申请号：EP01304817.8

申请日：2001-05-31

申请人： LATTICE SEMICONDUCTOR CORPORATION ,  The University of Kentucky Research Foundation

发明人： Abramovici, Miron ,  Stroud, Charles E. ,  Emmert, John M.

IPC分类号： G06F11/20 ,  G01R31/3185

CPC分类号： G01R31/318519 ,  G06F11/1428

摘要： A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into initial self-testing areas and a working area. Within the self-testing areas, programmable logic blocks (PLBs) of the FPGA are tested for faults. Upon the detection of one or more faults within the PLBs, the faulty PLBs are isolated and their modes of operation exhaustively tested. Partially faulty PLBs are allowed to continue operation in a diminished capacity as long as the faulty modes of operation do not prevent the PLBs from performing non-faulty system functions. After testing the programmable logic blocks in the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing, or continuously.

公开(公告)号：EP1170666A2

公开(公告)日：2002-01-09

申请号：EP01304817.8

申请日：2001-05-31

申请人： Agere Systems Guardian Corporation ,  The University of Kentucky Research Foundation

发明人： Abramovici, Miron ,  Stroud, Charles E. ,  Emmert, John M.

IPC分类号： G06F11/20 ,  G01R31/3185

CPC分类号： G01R31/318519 ,  G06F11/1428

摘要： A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into initial self-testing areas and a working area. Within the self-testing areas, programmable logic blocks (PLBs) of the FPGA are tested for faults. Upon the detection of one or more faults within the PLBs, the faulty PLBs are isolated and their modes of operation exhaustively tested. Partially faulty PLBs are allowed to continue operation in a diminished capacity as long as the faulty modes of operation do not prevent the PLBs from performing non-faulty system functions. After testing the programmable logic blocks in the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing, or continuously. Prior to relocating the initial self-testing areas, the initial self-testing areas are reconfigured to replace unusable faulty PLBs with spare PLBs. Spare PLBs are initially allocated throughout the working area. Specifically, each operational PLB within the working area is allocated an adjacent preferred spare PLB. Predetermined configurations of the FPGA utilizing the preferred spares are used to avoid the faulty PLBs. If the initially allocated spares are incapable of utilization, then a subsequent portion of the PLBs within the working area are allocated as spares and new replacement configurations determined. As the number of spare PLBs is diminished over time, additional spare PLBs are at some point necessarily removed from the self-testing areas. In this manner, the testing and roving capabilities of the self-testing area are also inevitably diminished. Eventually, roving, testing, and even operation of the FPGA will cease.

摘要翻译： 在正常在线操作期间利用增量重新配置的现场可编程门阵列（FPGA）的容错操作的方法包括将FPGA配置为初始自检区域和工作区域。 在自检区域内，FPGA的可编程逻辑块（PLB）被测试出故障。 在检测到PLB中的一个或多个故障之后，故障的PLB被隔离，并且其操作模式被彻底测试。 只要有故障的操作模式不能阻止PLB执行无故障的系统功能，部分故障的PLB就能够在能力下降的情况下继续运行。 在对初始自检区域中的可编程逻辑块进行测试之后，重新配置FPGA，使得工作区域的一部分成为随后的自检区域，并且初始自检区域的至少一部分取代了 工作区域。 换句话说，自检区域遍布FPGA，重复测试和重新配置的步骤，直到整个FPGA进行了测试，或者连续进行。 在重新设置初始自检区域之前，将重新配置初始自检区域，以用备用的PLB来替换不可用的故障小巴。 备用小巴最初分配在整个工作区。 具体来说，工作区域内的每个操作PLB被分配相邻的优选备用PLB。 使用优选备件的FPGA的预定配置用于避免故障的PLB。 如果初始分配的备件不能使用，则将工作区域内的PLB的后续部分分配为备件，并确定新的替换配置。 由于备用小巴的数目随时间而减少，所以额外的备用小巴在某些时候一定会从自检地区移走。 以这种方式，自检区的测试和流动能力也不可避免地减少了。 最终，FPGA的漫游，测试甚至操作将会停止。