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    Method and apparatus for securing configuration scan chains of a programmable device
    1.
    发明授权
    Method and apparatus for securing configuration scan chains of a programmable device 有权

    公开(公告)号：EP2830222B1

    公开(公告)日：2018-05-30

    申请号：EP14176522.2

    申请日：2014-07-10

    申请人： Altera Corporation

    发明人： Doshi, Alok Shreekant ,  Pedersen, Bruce B.

    IPC分类号： H03K19/177 ,  G01R31/3185

    CPC分类号： G06F21/76 ,  G01R31/318519 ,  G06F21/44 ,  H03K19/1776 ,  H03K19/17768

    摘要： Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the plurality of memory elements into the scan chain. Each scan enable activation element is actuated, to connect its respective subplurality of the plurality of memory elements into the scan chain, by a first enable signal common to more than one of the scan enable activation elements, and a second enable signal for that one of the scan enable activation elements. Such scan chain circuitry may be used for entering configuration data into a programmable integrated circuit device.

    Method and apparatus for securing configuration scan chains of a programmable device
    3.
    发明公开
    Method and apparatus for securing configuration scan chains of a programmable device 有权
    用于保护的可编程设备的方法和装置Konfigurationsabtastketten

    公开(公告)号：EP2830222A1

    公开(公告)日：2015-01-28

    申请号：EP14176522.2

    申请日：2014-07-10

    申请人： Altera Corporation

    发明人： Doshi, Alok Shreekant ,  Pedersen, Bruce B.

    IPC分类号： H03K19/177 ,  G01R31/3185

    CPC分类号： G06F21/76 ,  G01R31/318519 ,  G06F21/44 ,  H03K19/1776 ,  H03K19/17768

    摘要： Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the plurality of memory elements into the scan chain. Each scan enable activation element is actuated, to connect its respective subplurality of the plurality of memory elements into the scan chain, by a first enable signal common to more than one of the scan enable activation elements, and a second enable signal for that one of the scan enable activation elements. Such scan chain circuitry may be used for entering configuration data into a programmable integrated circuit device.

    摘要翻译： 到集成电路装置扫描链电路包括存储元件的多个，并且控制元件的复数。 控制元件中的每一个位于存储器元件的存储器元件的多元性可控制地连接到一个扫描链的多个respectivement者之间。 respectivement扫描使激活元件的多个控制的控制元件的多个用于连接存储元件的多个A respectivement子多个到扫描链中的子多个respectivement。 每个扫描使能激活元件被致动，到存储器元件的多个其respectivement子多个连接到扫描链，由第一使能公共信号给扫描的多于一个使激活元件，和第二使能为中的一个信号 扫描使能激活元件。 搜索扫描链电路可以被用于输入配置数据到可编程集成电路器件。

    MASK-PROGRAMMED INTEGRATED CIRCUITS HAVING TIMING AND LOGIC COMPATIBILITY TO USER-CONFIGURED LOGIC ARRAYS
    5.
    发明公开
    MASK-PROGRAMMED INTEGRATED CIRCUITS HAVING TIMING AND LOGIC COMPATIBILITY TO USER-CONFIGURED LOGIC ARRAYS 失效
    MASK随着集成电路和逻辑ZEITLICHER-容忍BENUTZERCONFIGIRIERBARE逻辑字段排定

    公开(公告)号：EP0688451A1

    公开(公告)日：1995-12-27

    申请号：EP94910853.0

    申请日：1994-03-11

    申请人： Xilinx, Inc.

    发明人： BUCH, Kiran, B. ,  LAW, Edwin, S. ,  CHU, Jakong, J.

    IPC分类号： G06F11 ,  G01R31 ,  G06F17 ,  H01L21

    CPC分类号： G01R31/318519 ,  G06F11/261 ,  G06F17/5068 ,  Y10S706/921

    摘要： Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays (10), without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip-flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) (10) is preserved by clustering together in the mask-configured integrated circuit (a gate array) (16) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area.

    Programmable logic module and architecture for field programmable gate array device
    6.
    发明公开
    Programmable logic module and architecture for field programmable gate array device 失效
    Programmierbarer Logikbaustein und Aufbaufüreine anwenderprogrammierbare Gatterfelderanordnung。

    公开(公告)号：EP0683565A1

    公开(公告)日：1995-11-22

    申请号：EP95303345.3

    申请日：1995-05-18

    申请人： ACTEL CORPORATION

    发明人： El-Ayat, Khaled A. ,  Kaptanoglu, Sinan ,  Chan, King W. ,  Plants, William C. ,  Lien, Jung-Cheun

    IPC分类号： H03K19/173

    CPC分类号： G01R31/2884 ,  G01R31/318516 ,  G01R31/318519 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

    摘要： A user-programmable gate array architecture includes an array of logic function modules (12) which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels (14-1 to 14-4;18-1 to 18-4), each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements (24). A local interconnect architecture comprising local interconnect channels (22-1 to 22-6) is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

    摘要翻译： 用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块（12）阵列。 包括多个水平和垂直通用互连通道（14-1至14-4; 18-1至18-4）的互连架构，每个通道互连通道（14-1至14-4; 18-1至18-4）均包含多个可能被分段的互连导体， 。 互连导体中的单个导体可由用户可编程互连元件（24）彼此连接并连接到逻辑功能模块的输入和输出。 包括本地互连通道（22-1至22-6）的本地互连架构也被施加在阵列上。 每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

    Programmable logic device
    8.
    发明公开
    Programmable logic device 失效
    可编程逻辑器件

    公开(公告)号：EP0227329A2

    公开(公告)日：1987-07-01

    申请号：EP86309319.1

    申请日：1986-11-28

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Agrawal, Om P. ,  Shankar, Kapil ,  Mubarak, Fares

    IPC分类号： H03K19/177

    CPC分类号： G01R31/318519 ,  G01R31/318516 ,  G01R31/318572 ,  H03K19/1736 ,  H03K19/17716 ,  H03K19/17744

    摘要： A device having a number of general registers each allocated an input / output port and a number internal "buried" state registers. A user-controlled signal permits observation of the contents of the buried state registers at an input/output port although these registers are not allocated an input! output port. Each register is connected to a logic circuit internal to the device by a dedicated feedback path so that all registers can be used to specify states in a state machine sequencer. A fuse-programmable XOR gate permits a user to control generation of signals at the ports by permitting enabling and disabling of an inverting output buffer. Asynchronous reset and synchronous preset of the registers is prov ided. In addition to the dedicated feedback paths, programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an external pin. The input/output circuit can be deployed in banks, each bank selectably receiving the same or a different clock. The registers can be preloaded via an internally-generated signal or from the external pins. In an alternative embodiment, a programmable AND array and a pair of programmable OR arrays, each serving one of the banks, provides a flexible programmable logic array device with observable buried states.

    摘要翻译： 具有多个通用寄存器的设备，每个通用寄存器分配一个输入/输出端口和多个内部“掩埋”状态寄存器。 用户控制的信号允许在输入/输出端口观察掩埋状态寄存器的内容，尽管这些寄存器没有被分配输入！ 输出端口。 每个寄存器通过专用反馈路径连接到设备内部的逻辑电路，以便可以使用所有寄存器指定状态机序列器中的状态。 熔丝可编程异或门允许用户通过允许和禁用反相输出缓冲器来控制端口处信号的产生。 提供寄存器的异步复位和同步预置。 除了专用的反馈路径外，还提供了可编程的反馈路径。 输出反相器可以通过内部信号或外部引脚选择使能。 输入/输出电路可以部署在银行中，每个银行可选择地接收相同或不同的时钟。 寄存器可以通过内部产生的信号或外部引脚进行预加载。 在一个替代实施例中，每个服务于一个存储体的可编程AND阵列和一对可编程OR阵列提供具有可观察埋置状态的灵活可编程逻辑阵列装置。

    Sensor zur Überwachung und Verfahren zur Fehleraufdeckung
    9.
    发明公开
    Sensor zur Überwachung und Verfahren zur Fehleraufdeckung 有权
    传感器用于监测和故障检测方法

    公开(公告)号：EP2804008A1

    公开(公告)日：2014-11-19

    申请号：EP13167804.7

    申请日：2013-05-15

    申请人： SICK AG

    发明人： Zwölfer, Ulrich ,  Müller, Lars ,  Neubauer, Dr., Matthias

    IPC分类号： G01R31/3185 ,  G01V8/00

    CPC分类号： G01R31/318519

    摘要： Es wird ein Sensor (10), insbesondere ein optoelektronischer Sensor, zur Überwachung eines Überwachungsbereichs (12) angegeben, mit einem Sensorelement (16) zur Erfassung von Überwachungsinformationen aus dem Überwachungsbereich (12) und mit einer sicheren Auswertungseinheit (26) zur Auswertung der Überwachungsinformationen, die ein FPGA (28) und eine Prüfeinheit (30) aufweist, um die eigene Funktion zu überprüfen. Dabei sind Logikelemente (50) des FPGA (28) in einen Testmodus umschaltbar, in dem die Logikelemente (50) zu mindestens einer Testkette (40) verbunden sind, und die Prüfeinheit (30) dafür ausgebildet ist, die Funktion des FPGA (28) während des Betriebs durch Umschalten auf den Testmodus mit Hilfe der mindestens einen Testkette (40) zu überprüfen.

    摘要翻译： 有一个传感器（10），尤其是一种光电传感器，提供了一种用于与传感器元件（16），用于检测从监视区域（12）的监视信息监视监视区域（12）和一个安全的评估单元（26），用于分析所述监视信息 具有FPGA（28）和检查单元（30），以验证其自身的功能。 这里，在测试模式下的FPGA（28）的逻辑元件（50）可切换，其中，所述逻辑单元（50）到至少一个测试链（40）连接，与所述检测单元（30）适于将所述FPGA的功能（28） 通过所述至少一个测试链（40）的装置切换到测试模式下的操作期间进行检查。

    Method and apparatus of reloading erroneous configuration data frames during configuration of PLDs
    10.
    发明公开
    Method and apparatus of reloading erroneous configuration data frames during configuration of PLDs 审中-公开
    可编程逻辑器件的配置过程中的方法和用于不正确的配置数据的装置herladen

    公开(公告)号：EP1411431A3

    公开(公告)日：2010-10-20

    申请号：EP03020154.5

    申请日：2003-09-05

    申请人： Sicronic Remote KG, LLC

    发明人： Goel, Ashish Kumar ,  Khanna, Namerita ,  Aggarwal, Davinder

    IPC分类号： G06F11/14 ,  G06F17/50

    CPC分类号： G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

    摘要： The invention provides an improved method and apparatus for reloading only those frames in which errors are detected during the FPGA configuration. A configuration data frame for a FPGA is sumultaneously loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value 'n'. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and recheked for errors. If no error os detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.