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公开(公告)号:EP4387424A1
公开(公告)日:2024-06-19
申请号:EP23204564.1
申请日:2023-10-19
申请人: LG Display Co., Ltd.
发明人: CHOI, Jaeyi
IPC分类号: H10K59/131
CPC分类号: H10K59/131
摘要: A display panel (110) according to embodiments of the disclosure may comprise a substrate (SUB) in which a display area (DA) and a non-display area (NDA) are divided, a gate driving circuit (130) disposed on the substrate (SUB) and disposed in a gate driving circuit area (GIPA) within the non-display area (NDA), a plurality of gate clock lines (GCLKL) disposed on the substrate (SUB) and disposed in a first line area (LA1) positioned outside the gate driving circuit area (GIPA) in the non-display area (NDA), an overcoat layer (OC) disposed on the plurality of gate clock lines (GCLKL) and the gate driving circuit (130), a cathode electrode (CE) disposed in the display area (DA) and extending to the non-display area (NDA), and a load deviation compensation pattern (COMP) overlapping the plurality of gate clock lines (GCLKL).
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公开(公告)号:EP4425472A1
公开(公告)日:2024-09-04
申请号:EP24160244.0
申请日:2024-02-28
申请人: LG Display Co., Ltd.
发明人: CHOI, Jaeyi , CHOI, SooHong , SHIN, HongJae
IPC分类号: G09G3/3266 , G09G3/3233
CPC分类号: G09G3/3266 , G09G2300/042620130101 , G09G2330/0420130101 , G09G2320/029520130101 , G09G2320/04520130101 , G09G3/3233
摘要: The present disclosure relates to a display panel and a display device, and can provide a display panel and a display device that have a clock signal line arrangement structure that is advantageous to electrostatic discharge.
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