摘要:
Disclosed is a method of manufacturing a solar cell. The method includes forming a protective (20, 24, 40) film using an insulation film over a semiconductor substrate, the semiconductor substrate including a base area (110) of a first conductive type and formed of crystalline silicon. The forming of the protective film includes a heat treatment process performed at a heat treatment temperature of 600 degrees Celsius or more under a gas atmosphere including a halogen gas, which has a halogen element.
摘要:
A solar cell comprises: a semiconductor substrate (10); a tunneling layer (20) formed on a surface of the semiconductor substrate; a p-type conductive region (32) and a n-type conductive region (34) formed on the tunneling layer, the p- and n-type conductive regions being disposed next to each other in a direction parallel to the surface of the semiconductor substrate and being separated by a barrier region (36); and an electrode structure (42, 44) electrically connected to the p- and n-type conductive regions, wherein the barrier region includes an intrinsic semiconductor portion (30c) and a buffer portion (22c) located between the intrinsic semiconductor portion and the tunneling layer, the buffer portion having stronger electrical insulating property than the intrinsic semiconductor portion.
摘要:
Disclosed is a method of manufacturing a solar cell. The method includes forming a protective (20, 24, 40) film using an insulation film over a semiconductor substrate, the semiconductor substrate including a base area (110) of a first conductive type and formed of crystalline silicon. The forming of the protective film includes a heat treatment process performed at a heat treatment temperature of 600 degrees Celsius or more under a gas atmosphere including a halogen gas, which has a halogen element.
摘要:
A solar cell comprises: a semiconductor substrate (10); a tunneling layer (20) formed on a surface of the semiconductor substrate; a p-type conductive region (32) and a n-type conductive region (34) formed on the tunneling layer, the p- and n-type conductive regions being disposed next to each other in a direction parallel to the surface of the semiconductor substrate and being separated by a barrier region (36); and an electrode structure (42, 44) electrically connected to the p- and n-type conductive regions, wherein the barrier region includes an intrinsic semiconductor portion (30c) and a buffer portion (22c) located between the intrinsic semiconductor portion and the tunneling layer, the buffer portion having stronger electrical insulating property than the intrinsic semiconductor portion.