公开(公告)号：EP0676116A4

公开(公告)日：1999-05-26

申请号：EP94930821

申请日：1994-10-18

申请人： LSI LOGIC CORP

发明人： AULD DAVID R

IPC分类号： H04N11/04 ,  H03M7/00 ,  H04N7/08 ,  H04N7/081 ,  H04N7/26 ,  H04N7/50 ,  H04N9/475 ,  H04N7/12 ,  H04N11/02

CPC分类号： H04N19/61 ,  H04N19/00 ,  H04N19/70

摘要： A novel synchronization scheme for use in connection with digital signal video decoder (58) comprises a pre-parser (52), a channel buffer (54), and a post-parser (56). The pre-parser (52) synchronizes to a multiplexed system bitstream received from a fixed rate channel (50). The video bitstream component of a multiplexed system bitstream is then extracted and synchronized prior to being transferred bit-serially from the pre-parser (52) to a channel buffer (54). The post-parser (56) is coupled to the channel buffer (54) and to a video decoder (58) in a series configuration. The post-parser (56) separates the various layers of video data from the video bitstream component. The post-parser (56) performs a translation operation on the video bitstream component and converts the bitstream data into symbol data. The symbol data is subsequently processed by the video decoder (58) so as to reconstruct an originally encoded picture or frame. Preferably, the multiplexed system bitstream data structure conforms to some format agreed upon among video digital businesses involved in transmission and reception. In accordance with one aspect of the present invention, the pre-parser (52) and the post-parser (56) operate independent of each other, and operate at different processing rates.

公开(公告)号：EP0683955A4

公开(公告)日：1999-03-03

申请号：EP94931904

申请日：1994-10-18

申请人： LSI LOGIC CORP

发明人： AULD DAVID R

IPC分类号： H04N5/907 ,  H04N7/173 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N19/00 ,  H04N21/43 ,  H04N21/433 ,  H04N21/438 ,  H04N21/44

CPC分类号： H04N21/44004 ,  H04N19/152 ,  H04N19/423 ,  H04N19/427 ,  H04N19/50 ,  H04N19/61 ,  H04N21/4302 ,  H04N21/4382

摘要： A novel channel buffer management scheme for a video decoder minimizes the amount of memory allocated to buffer a video bitstream received from a transmission channel. A channel buffer accumulates picture data encoded in a video bitstream received from a fixed rate channel. Picture data is read out of the channel buffer by a video decoder immediately after a predetermined or expected amount of bitstream data is received by the channel buffer. Picture decoding, reconstructing, and displaying operations are synchronized to permit the transfer of picture data from the channel buffer to the decoder whenever all of the data bits comprising a picture are received in the channel buffer. A microcontroller monitors and regulates the operation of the novel channel buffer management scheme to avoid overflow or underflow of bitstream data in the channel buffer. In accordance with one aspect of the present invention, a display controller and picture reconstruction means are fabricated as an monolithic integrated circuit device.