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11 条记录 (耗时 0.035 秒)

    PLANARIZED PROCESS FOR FORMING VIAS IN SILICON WAFERS.
    2.
    发明公开
    PLANARIZED PROCESS FOR FORMING VIAS IN SILICON WAFERS. 失效
    PLANARISIERUNGSVERFAHRENFÜRDIE HERSTELLUNG VON KONTAKTLOCHERN在SILIZIUMKÖRPERN。

    公开(公告)号：EP0311627A4

    公开(公告)日：1989-12-13

    申请号：EP87904195

    申请日：1987-06-11

    申请人： LSI LOGIC CORP ,  PASCH NICHOLAS F

    发明人： PASCH NICHOLAS F

    IPC分类号： H01L21/3205 ,  H01L21/306 ,  H01L21/768

    CPC分类号： H01L21/76801 ,  H01L21/76819

    摘要： A process for forming vias in semiconductor structures includes the step of forming a pillar (32) on an underlying dielectric layer (26) prior to deposition of the metallization layer (M1). The pillar (32) is located above the diffusion region (18) preferably and serves to provide substantially equal distances or heights (d1, d2) for etching vias from the top planarized surface (34) to the metallization layer (M1) deposited over the field oxide region (16) and over the diffusion region (18).

    摘要翻译： 用于在半导体结构中形成通孔的工艺包括在沉积金属化层（M1）之前在下面的电介质层（26）上形成柱（32）的步骤。 柱（32）优选位于扩散区（18）上方并且用于提供用于从顶部平坦化表面（34）到沉积在其上的金属化层（M1）的蚀刻通孔提供基本相等的距离或高度（d1，d2） 场氧化物区域（16）和扩散区域（18）之上。

    DROOP-FREE QUASI-CONTINUOUS RECONSTRUCTION FILTER INTERFACE
    3.
    发明公开
    DROOP-FREE QUASI-CONTINUOUS RECONSTRUCTION FILTER INTERFACE 审中-公开
    DROOP免费的准连续重建滤波器接口

    公开(公告)号：EP1131889A4

    公开(公告)日：2004-10-27

    申请号：EP00930841

    申请日：2000-05-24

    申请人： LSI LOGIC CORP

    发明人： SHENG SAMUEL W ,  CONROY CORMAC S

    IPC分类号： H03M1/66 ,  H03H19/00 ,  H03M1/06 ,  H03M1/08 ,  H04B3/04 ,  H04J11/00

    CPC分类号： H03M1/0631 ,  H03H19/004 ,  H03M1/0614 ,  H03M1/66

    摘要： A reconstruction filter is described. An input is configured to receive an output signal from a digital to analog converter (400). An input sampling circuit (402) is operative to store a sample of the output signal from the digital to analog converter (400). An input pulse generating switch (404) that generates a pulse, the energy of the pulse being determined by the sample of the output signal from the digital to analog converter (400). An amplifier (410) receives the pulse at an amplifier input and provides an output signal at an amplifier output so that an output signal is produced that reduces distortion caused by imperfections in digital to analog converter (400).

    IMPROVED PLANARIZATION PROCESS.
    5.
    发明公开
    IMPROVED PLANARIZATION PROCESS. 失效
    规划体系。

    公开(公告)号：EP0346423A4

    公开(公告)日：1990-04-10

    申请号：EP89900518

    申请日：1988-11-18

    申请人： LSI LOGIC CORP

    发明人： PATRICK ROGER

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768

    CPC分类号： H01L21/76819 ,  Y10S148/051 ,  Y10S148/081 ,  Y10S148/131

    摘要： A planarization process and the resulting structure are disclosed. Dielectric layers (22/24) are successively deposited over nonplanar first level contacts (18/20) and patterned to form interlevel vias where interconnect plugs to first level contacts are desired. A conductive layer (36) which fills the vias conformally is covered with a photoresist layer (38). The layers (38, 36, 24) are then etched at substantially the same rate to provide planarized contact plugs (28) which are planar with the interlevel dielectric (22/24).

    A TWO-PART SYNCHRONIZATION SCHEME FOR DIGITAL VIDEO DECODERS.
    6.
    发明公开
    A TWO-PART SYNCHRONIZATION SCHEME FOR DIGITAL VIDEO DECODERS. 失效
    两个SYNCHRONIZATIONSSCHEMA数字视频解码器。

    公开(公告)号：EP0676116A4

    公开(公告)日：1999-05-26

    申请号：EP94930821

    申请日：1994-10-18

    申请人： LSI LOGIC CORP

    发明人： AULD DAVID R

    IPC分类号： H04N11/04 ,  H03M7/00 ,  H04N7/08 ,  H04N7/081 ,  H04N7/26 ,  H04N7/50 ,  H04N9/475 ,  H04N7/12 ,  H04N11/02

    CPC分类号： H04N19/61 ,  H04N19/00 ,  H04N19/70

    摘要： A novel synchronization scheme for use in connection with digital signal video decoder (58) comprises a pre-parser (52), a channel buffer (54), and a post-parser (56). The pre-parser (52) synchronizes to a multiplexed system bitstream received from a fixed rate channel (50). The video bitstream component of a multiplexed system bitstream is then extracted and synchronized prior to being transferred bit-serially from the pre-parser (52) to a channel buffer (54). The post-parser (56) is coupled to the channel buffer (54) and to a video decoder (58) in a series configuration. The post-parser (56) separates the various layers of video data from the video bitstream component. The post-parser (56) performs a translation operation on the video bitstream component and converts the bitstream data into symbol data. The symbol data is subsequently processed by the video decoder (58) so as to reconstruct an originally encoded picture or frame. Preferably, the multiplexed system bitstream data structure conforms to some format agreed upon among video digital businesses involved in transmission and reception. In accordance with one aspect of the present invention, the pre-parser (52) and the post-parser (56) operate independent of each other, and operate at different processing rates.

    METHOD FOR THE CONTROLLED FORMATION OF VOIDS IN DOPED GLASS DIELECTRIC FILMS
    7.
    发明公开
    METHOD FOR THE CONTROLLED FORMATION OF VOIDS IN DOPED GLASS DIELECTRIC FILMS 失效
    方法在掺杂电介质玻璃层孔洞的受控GENERATION

    公开(公告)号：EP0686304A4

    公开(公告)日：1997-10-22

    申请号：EP94911413

    申请日：1994-02-16

    申请人： LSI LOGIC CORP

    发明人： MALLON THOMAS G ,  KAO CHI-YI ,  HSIA WEI-JEN ,  SHIMODA ATSUSHI

    IPC分类号： H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/473

    CPC分类号： H01L21/31051 ,  H01L21/76819 ,  H01L21/7682

    摘要： A method is provided for the controlled formation of voids (18) in integrated circuit doped glass dielectric films (13, 19). The film (13, 19) can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate (11) on which conductors (15, 16) are formed, depositing a first layer (13) of doped glass to a thickness in a predetermined ratio to the size of the space (17) between conductors (15, 16), reflowing the first doped glass layer (13), applying one or more additional doped glass layers (19) to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer (19). The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.

    INTEGRATED NETWORK BROWSER CHIP, NETWORK BROWSER SYSTEM, AND METHOD FOR NETWORK DATA COMMUNICATION
    8.
    发明公开
    INTEGRATED NETWORK BROWSER CHIP, NETWORK BROWSER SYSTEM, AND METHOD FOR NETWORK DATA COMMUNICATION 失效
    集成网络浏览器页面芯片，网络浏览器系统和网络数据通信方法

    公开(公告)号：EP0896703A4

    公开(公告)日：2007-07-04

    申请号：EP96942838

    申请日：1996-11-27

    申请人： LSI LOGIC CORP

    发明人： DANNE JOHN P ,  HALLA BRIAN LESTER ,  ANG PENG HUAT

    IPC分类号： G06F13/00 ,  G06G3/10 ,  G06F15/78 ,  G06F17/30 ,  H04L29/06

    CPC分类号： G06F15/7842 ,  H04L29/06

    摘要： An integrated network browser controller chip (218), network device (202), and network system (204) is disclosed for data transmission and reception over a network. The network browser chip includes a microprocessor (212) for operating a network browser program to connect the network browser chip to the Internet, an on-chip memory for storing the network browser (216) and the operating system program, a communications interface (210) for connecting the network browser chip to the Internet, and a user interface (234) for transferring user instructions to the network browser chip and for transferring data from the network to the user. A network browser device is further disclosed which utilizes a single integrated network browser controller chip (218) for connecting the device to the network (204). A non-networking electronic device is further disclosed which is modified with the integrated network browser controller chip (212) to enable data transmission and reception over the network.

    MANAGEMENT OF CHANNEL BUFFER IN VIDEO DECODERS.
    9.
    发明公开
    MANAGEMENT OF CHANNEL BUFFER IN VIDEO DECODERS. 失效
    KANALPUFFERSTEUERUNG IN VIDEODEKODERN。

    公开(公告)号：EP0683955A4

    公开(公告)日：1999-03-03

    申请号：EP94931904

    申请日：1994-10-18

    申请人： LSI LOGIC CORP

    发明人： AULD DAVID R

    IPC分类号： H04N5/907 ,  H04N7/173 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N19/00 ,  H04N21/43 ,  H04N21/433 ,  H04N21/438 ,  H04N21/44

    CPC分类号： H04N21/44004 ,  H04N19/152 ,  H04N19/423 ,  H04N19/427 ,  H04N19/50 ,  H04N19/61 ,  H04N21/4302 ,  H04N21/4382

    摘要： A novel channel buffer management scheme for a video decoder minimizes the amount of memory allocated to buffer a video bitstream received from a transmission channel. A channel buffer accumulates picture data encoded in a video bitstream received from a fixed rate channel. Picture data is read out of the channel buffer by a video decoder immediately after a predetermined or expected amount of bitstream data is received by the channel buffer. Picture decoding, reconstructing, and displaying operations are synchronized to permit the transfer of picture data from the channel buffer to the decoder whenever all of the data bits comprising a picture are received in the channel buffer. A microcontroller monitors and regulates the operation of the novel channel buffer management scheme to avoid overflow or underflow of bitstream data in the channel buffer. In accordance with one aspect of the present invention, a display controller and picture reconstruction means are fabricated as an monolithic integrated circuit device.

    Method for interleaving network traffic over serial lines
    10.
    发明公开
    Method for interleaving network traffic over serial lines 失效
    在串行链路上交错的网络流量的方法

    公开(公告)号：EP0785642A3

    公开(公告)日：1998-11-18

    申请号：EP97300266

    申请日：1997-01-17

    申请人： LSI LOGIC CORP

    发明人： DAANE JOHN P

    IPC分类号： G11B20/12 ,  H04J3/00 ,  H04J3/16

    CPC分类号： H04J3/16

    摘要： A method (30) for interleaving a plurality of formatted data streams (10) on a network (20) wherein the formatted data streams (10) are divided into a further plurality of time bites (44) and synch characters (48) are added thereto in an add synch character operation (46). The time bites (44) are then transmitted as an assembled serial data stream (39) in a serializer (31). In a deserializer (32) the time bits (44) are reconstituted into the separate individual formatted data streams (10).