公开(公告)号：EP4383573A1

公开(公告)日：2024-06-12

申请号：EP23213468.4

申请日：2023-11-30

申请人： Lattice Semiconductor Corporation

发明人： SHAHBAZI, Maryam ,  SHARPE-GEISLER, Bradley A. ,  GUNARATNA, Senani ,  MCLAURY, Loren L.

IPC分类号： H03K19/17736 ,  H03K19/17764

CPC分类号： H03K19/17764 ,  H03K19/17744 ,  H03K19/1774

摘要： Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices, PLDs. In one example, a method comprises configuring an intellectual property, IP, block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block, determining a delay associated with the first clock signal between a first input and the first component, configuring a programmable logic cell, PLC, to receive a second clock signal and output the first data signal to the IP block, determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, and configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block. Additional systems and methods are also provided.