公开(公告)号：EP1631980B1

公开(公告)日：2018-08-15

申请号：EP04718583.0

申请日：2004-03-08

申请人： Luxtera, Inc. ,  Gunn III, Lawrence C.

发明人： GUNN III, Lawrence, C. ,  CAPELLINI, Giovanni ,  RATTIER, Maxime, J. ,  PINGUET, Thierry, J.

IPC分类号： H01L21/8238 ,  H01L21/20 ,  H01L21/205 ,  H01L27/144

CPC分类号： H01L21/823878 ,  H01L21/8238 ,  Y10S438/958

摘要： Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.

公开(公告)号：EP1631980A2

公开(公告)日：2006-03-08

申请号：EP04718583.0

申请日：2004-03-08

申请人： Luxtera, Inc. ,  Gunn, Lawrence C. III

发明人： GUNN III, Lawrence, C. ,  CAPELLINI, Giovanni ,  RATTIER, Maxime, J. ,  PINGUET, Thierry, J.

IPC分类号： H01L21/20

CPC分类号： H01L21/823878 ,  H01L21/8238 ,  Y10S438/958

摘要： Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.