公开(公告)号：EP4328973A3

公开(公告)日：2024-05-29

申请号：EP23220365.3

申请日：2018-10-30

申请人： INTEL Corporation

发明人： HO, Byron ,  HATTENDORF, Michael L. ,  AUTH, Christopher P.

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/092 ,  H01L29/165 ,  H01L29/417

CPC分类号： H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/66545 ,  H01L27/0886 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/7854 ,  H01L28/20 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823475 ,  H01L23/485 ,  H01L2224/7320420130101 ,  H01L21/3086 ,  H01L21/0337

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

公开(公告)号：EP3252814B1

公开(公告)日：2018-12-26

申请号：EP17173928.7

申请日：2017-06-01

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： LI, Yong

IPC分类号： H01L27/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78

CPC分类号： H01L27/0274 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0255 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7816 ,  H01L29/785

摘要： An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and a surface portion of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.

公开(公告)号：EP1612861B1

公开(公告)日：2018-10-03

申请号：EP03816642.7

申请日：2003-04-10

申请人： Fujitsu Semiconductor Limited

发明人： EMA, Taiji, c/o FUJITSU LIMITED ,  KOJIMA, Hideyuki, c/o FUJITSU LIMITED ,  ANEZAKI, Toru, c/o FUJITSU LIMITED

IPC分类号： H01L27/088

CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

摘要： Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.

公开(公告)号：EP3311418A1

公开(公告)日：2018-04-25

申请号：EP15895827.2

申请日：2015-06-19

申请人： Intel Corporation

发明人： MEHANDRU, Rishabh ,  MURTHY, Anand S. ,  GHANI, Tahir ,  GLASS, Glenn A. ,  JAMBUNATHAN, Karthik ,  MA, Sean T. ,  WEBER, Cory E.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

摘要： Techniques are disclosed for resistance reduction in p-MOS transistors having epitaxially grown boron-doped silicon germanium (SiGe:B) S/D regions. The techniques can include growing one or more interface layers between a silicon (Si) channel region of the transistor and the SiGe:B replacement S/D regions. The one or more interface layers may include: a single layer of boron-doped Si (Si:B); a single layer of SiGe:B, where the Ge content in the interface layer is less than that in the resulting SiGe:B S/D regions; a graded layer of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage; or multiple stepped layers of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage at each step. Inclusion of the interface layer(s) reduces resistance for on-state current flow.

公开(公告)号：EP3306665A2

公开(公告)日：2018-04-11

申请号：EP17195405.0

申请日：2017-10-09

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： LI, Yong

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L27/0886 ,  H01L21/0276 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/12 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66818

摘要： A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a plurality of fins on a substrate including an NMOS region and a PMOS region adjacent to the NMOS region; forming an N-type well in the PMOS region and a P-type well in the NMOS region of the substrate; forming a protective sidewall to cover an upper portion of a sidewall surface of each fin in each of the NMOS region and PMOS region and to expose a lower portion of the sidewall surface of each fin; removing a partial width of the lower portion of the fin using the protective sidewall as an etch mask; removing the protective sidewall; and forming an isolation structure at least by oxidizing the remaining lower portion of the fin and having a top surface lower than the neighboring upper portions of the fins.

摘要翻译： 提供半导体结构和制造方法。 制造方法包括：在包括NMOS区域和与NMOS区域相邻的PMOS区域的衬底上提供多个鳍; 在PMOS区域中形成N型阱，在衬底的NMOS区域中形成P型阱; 形成保护侧壁以覆盖NMOS区域和PMOS区域中的每一个中的每个鳍​​状物的侧壁表面的上部并且暴露每个鳍状物的侧壁表面的下部; 使用保护性侧壁作为蚀刻掩模来去除鳍状物的下部的部分宽度; 去除保护侧壁; 以及至少通过氧化鳍状物的剩余下部并且具有比鳍状物的相邻上部低的顶表面来形成隔离结构。

公开(公告)号：EP1693897B1

公开(公告)日：2018-03-07

申请号：EP05010736.6

申请日：2005-05-18

申请人： Fujitsu Semiconductor Limited

发明人： Tamura, Naoyoshi ,  Shimamune, Yosuke ,  Hatada, Akiyoshi ,  Katakami, Akira ,  Shima, Masashi

IPC分类号： H01L29/78 ,  H01L29/45 ,  H01L29/165 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate electrode, a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films epitaxially to the silicon substrate so as to be enclosed respectively by the source and drain regions, each of the SiGe mixed crystal regions being grown to a level above a level of a gate insulation film interface between the gate insulation film and the silicon substrate, wherein there is provided a compressive stress film at respective top surfaces of the SiGe mixed crystal regions.

公开(公告)号：EP3179507A3

公开(公告)日：2017-08-02

申请号：EP16199544.4

申请日：2016-11-18

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： LI, Yong

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

摘要： The present invention provides HKMG transistor structures and fabrication methods thereof. An exemplary method includes providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening in the first region and a second opening in the second region over; forming a gate dielectric layer on a side surface of the first opening and a portion of the base substrate in the first opening and on a side surface of the second opening and a portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer.

摘要翻译： 本发明提供HKMG晶体管结构及其制造方法。 一种示例性方法包括提供具有第一区域和第二区域的基础衬底; 形成在所述第一区域中具有第一开口并且在所述第二区域中具有第二开口的电介质层; 在所述第一开口的侧表面上以及所述基底基板的所述第一开口中和所述第二开口的侧表面上以及所述基底基板的所述第二开口中的一部分上形成栅极电介质层; 在第一开口中填充牺牲层; 在第二开口中形成第二功函数层，并在第二功函数层上形成第二栅电极层; 去除牺牲层; 以及在第一开口中形成第一功函数层，并在第一功函数层上形成第一栅电极层。

公开(公告)号：EP3188245A1

公开(公告)日：2017-07-05

申请号：EP16205796.2

申请日：2016-12-21

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： XIE, Xinyun

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/225 ,  H01L29/06 ,  H01L21/265

CPC分类号： H01L29/0638 ,  H01L21/26513 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66795 ,  H01L29/7851

摘要： A method is provided for fabricating a FinFET. The method includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate, wherein a position of the hard mask layer may corresponds to a position of subsequently formed fin; forming a doping region in the semiconductor substrate by using the hard mask layer as a mask to perform an anti-punch-through ion implantation process; forming an anti-punch-through region by performing an annealing process onto the doping region, such that impurity ions in the doping region diffuse into the semiconductor substrate under the hard mask layer; and forming a trench by using the hard mask layer as a mask to etch the semiconductor substrate and the doping region, wherein the semiconductor substrates between the adjacent trenches constitutes a fin.

摘要翻译： 提供了一种制造FinFET的方法。 该方法包括提供半导体衬底; 在半导体衬底上形成硬掩模层，其中硬掩模层的位置可对应于随后形成的鳍的位置; 通过使用硬掩模层作为掩模在半导体衬底中形成掺杂区，以执行抗穿通离子注入工艺; 通过对所述掺杂区域进行退火处理，形成反冲穿区域，使得所述掺杂区域中的杂质离子扩散进入所述硬掩模层下方的所述半导体衬底; 以及通过使用硬掩模层作为掩模来形成沟槽，以蚀刻半导体衬底和掺杂区域，其中相邻沟槽之间的半导体衬底构成鳍。

公开(公告)号：EP3080844A1

公开(公告)日：2016-10-19

申请号：EP14869386.4

申请日：2014-12-12

申请人： Texas Instruments Incorporated

发明人： LIM, Kwan-Yong ,  BLATCHFORD, James, Walter ,  EKBOTE, Shashank, S. ,  CHOI, Younsung

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

摘要： An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

摘要翻译： 在间隙中形成有与MOS晶体管邻接的MOS晶体管和与MOS晶体管相邻的场氧化物上的栅极结构和外延源极/漏极与场氧化物之间的间隙的集成电路。 在暴露的外延源/漏区上形成金属硅化物。 在集成电路上形成CESL，并且在CESL上形成PMD层。 通过PMD层和CESL形成接触以与外延源极/漏极区上的金属硅化物形成电连接。

公开(公告)号：EP2044626B1

公开(公告)日：2015-07-22

申请号：EP07799114.9

申请日：2007-06-27

申请人： Intel Corporation

发明人： KAMGAING, Telesphor

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L23/58 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/764

CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/76898 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00