公开(公告)号：EP1475839A1

公开(公告)日：2004-11-10

申请号：EP03705200.8

申请日：2003-02-14

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： OGAWA, Hisashi ,  NAKAOKA, Hiroaki ,  KAJIYA, Atsuhiro ,  HASHIMOTO, Shin ,  EGASHIRA, Kyoko

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897

摘要： A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a , and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

摘要翻译： 存储单元晶体管和平面电容器被提供在存储区域中，并且CMOS器件的两个晶体管被提供在逻辑电路区域中。 平面电容器的电容电介质15和平板电极16b设置在与浅沟槽隔离12a共享的沟槽上方，并且沟槽的上部填充有电容电介质15和平板电极16b。 作为存储节点的n型扩散层19形成为其端部区域沿着沟槽的上部的一侧延伸到与浅沟槽隔离部12a重叠的衬底的区域。 用作电容器的基板的一部分的面积可以增加而不增加基板面积。