摘要:
The conventional method of limiting the number of receiving apparatus has a problem that if the limited number of appliances is reduced to limit distribution to unspecified appliances outside a home, distribution to appliances in the home is limited unnecessarily largely, and that if the limited number of appliances is increased, distribution to appliances outside the home cannot be sufficiently limited. At least one receiving apparatus, e.g., digital television sets and PCs, connected to a network and capable of receiving and using predetermined data, and a transmitting apparatus, e.g., an AV server for transmitting the data to the receiving apparatus via the network are provided. Use of the data on the network is managed on the basis of the transmission time required for transmission of predetermined information between the transmitting apparatus and the receiving apparatus.
摘要:
Different from typical signal processing which employs a feedback control, by adopting a demodulating circuit employing AFC, which is not affected by a comb filter, the response characteristic against jitter is improved and a down converted chrominance signal can be demodulated with a good accuracy. therefore, the noise rejection effect by a comb filter is improved, the detecting accuracy of the residual phase error is also improved, and the S/N ratio of the phase is improved by combining feedforward APC compensation with a velocity error, and this results in a much improved picture quality.
摘要:
In the case that a bridge unit is connected to a network such as an IEEE 1394 bus, the desire of copyright holders for limitation on the number of apparatuses that can receive a signal cannot be met. The invention is characterized by providing at least one reception unit, or more, that receives and utilizes data requiring copyright protection, connected to a network and by providing a transmission unit 20 for transmitting data requiring copyright protection to a reception unit by utilizing a network, wherein the transmission unit 20 has an authentication means 23 on the transmission side for carrying out authentication for a reception unit and an authentication number counting means 24 for counting the authentication number that is the number of the authentications carried out by the authentication means 23 on the transmission side while the reception unit has an authentication means on the reception side for carrying out authentication for the authentication means on the transmission side and wherein the above authentication number is limited.
摘要:
A reproduced signal from a recording medium 1 is equalized at partial response (1, 0, -1) by a reproducing equalizer 3, and is converted into a reproduced and equalized signal. A clock reproducing circuit 4 issues a reproduced clock synchronized with the timing of data identification, and applies it to a phase adjusting circuit 5. A phase control signal generating circuit 6A detects a specific pattern from a reproduced digital signal issued from an A/D converter 7, and the advance or delay amount of phase of the reproduced clock is detected by the amplitude or distribution of the sampling value. This phase deviation amount is given to the phase adjusting circuit 5 as a phase control signal. The phase adjusting circuit 5 given a delayed clock to the A/D converter 7, and controls to A/D convert the reproduced signal at correct timing.
摘要:
A reproduced signal from a recording medium 1 is equalized at partial response (1, 0, -1) by a reproducing equalizer 3, and is converted into a reproduced and equalized signal. A clock reproducing circuit 4 issues a reproduced clock synchronized with the timing of data identification, and applies it to a phase adjusting circuit 5. A phase control signal generating circuit 6A detects a specific pattern from a reproduced digital signal issued from an A/D converter 7, and the advance or delay amount of phase of the reproduced clock is detected by the amplitude or distribution of the sampling value. This phase deviation amount is given to the phase adjusting circuit 5 as a phase control signal. The phase adjusting circuit 5 given a delayed clock to the A/D converter 7, and controls to A/D convert the reproduced signal at correct timing.