公开(公告)号：EP0974197A1

公开(公告)日：2000-01-26

申请号：EP98960389.9

申请日：1998-11-19

申请人： MICROCHIP TECHNOLOGY INC.

发明人： WOJEWODA, Igor ,  CHIAO, Jennifer

IPC分类号： H03L7/10

CPC分类号： H03L7/12

摘要： A phase-locked loop (PLL) circuit has a phase comparator for comparing the phases of a local clock frequency and a reference frequency to generate a control signal indicative of a direction of adjustment of the local clock frequency for reducing the phase difference between the two frequencies. A voltage controlled oscillator (VCO) of the PLL responds to application of a control voltage thereto to generate an oscillation signal frequency from which the local clock frequency is derived. A loop filter responds to the control signal from the phase comparator to develop a control voltage for application to the VCO to adjust the local clock frequency in the direction indicated by the control signal to reduce the relative phase difference. The loop filter has a start-up circuit for detecting a selected edge of a cycle of the reference frequency after a predetermined number of cycles following commencement of operation or reset of the PLL circuit as being indicative of stabilization of the reference frequency, and is responsive to detection of such selected edge for promptly producing a linear boost of the control voltage from an initial level of substantially zero volts to a predetermined pull-up level exceeding the level of control voltage required to achieve phase locking. This reduces the time interval required to achieve phase locking, measured from the selected cycle edge. The loop filter is also responsive to the control voltage reaching the pull-up level to incrementally reduce the control voltage to the level required to achieve phase locking.

公开(公告)号：EP1066651A2

公开(公告)日：2001-01-10

申请号：EP99965330.6

申请日：1999-12-20

申请人： MICROCHIP TECHNOLOGY INC.

发明人： YACH, Randy, L. ,  WOJEWODA, Igor

IPC分类号： H01L27/08 ,  H01L29/92

CPC分类号： H01L27/0805

摘要： A matching capacitor array is implemented on a single, monolithic integrated circuit. The array fastures a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.

公开(公告)号：EP1086466A1

公开(公告)日：2001-03-28

申请号：EP00917817.9

申请日：2000-03-09

申请人： MICROCHIP TECHNOLOGY INC.

发明人： WOJEWODA, Igor ,  TRIECE, Joseph, W.

IPC分类号： G11C16/22 ,  G11C29/00 ,  G06F1/22

CPC分类号： G11C16/225 ,  G06F9/24 ,  G06F9/30101 ,  G11C16/22

摘要： A microcontroller having a memory programmable in user mode. The microcontroller contains circuitry for detecting whether a programming level voltage has been activated. Also included is a Longwrite enable register containing an enable bit for enabling/disabling programming of the memory. When the register contains the bit indicating programming as enabled, and the programming level voltage is detected, the microcontroller allows the program memory to be programmed. The programming can take place in user mode. The programming level voltage signal is also used to detect whether to enter into a test mode. Programming of the program memory is also possible in the test mode. The invention is also directed to a method for operating a microcontroller for controlling programming of the program memory. The microcontroller according to the invention allows increased functionality by detecting whether to enter the test mode without the requirement of a test mode select input signal.