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公开(公告)号：EP3709129B1
公开(公告)日：2023-03-01
申请号：EP20163094.4
申请日：2020-03-13
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公开(公告)号：EP3629127A1
公开(公告)日：2020-04-01
申请号：EP19166370.7
申请日：2019-03-29
申请人： Quanta Computer Inc.
摘要： The present disclosure provides a system and method for dynamically defining a specific input pin of a management controller (e.g., a baseboard management controller (BMC)) of a server system in response to a new device being plugged into the server system. The new device comprises one of a power supply unit (PSU), an automatic transfer switch (ATS), or a battery backup unit (BBU) of the server system. In some implementations, the PSU, the ATS, and the BBU are modularized into a plurality of ATS modules, a plurality of PSU modules, and a plurality of BBU modules, respectively. Each of the plurality of ATS modules, the plurality of PSU modules, and the plurality of BBU modules has substantially the same physical size.
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公开(公告)号：EP3152670A1
公开(公告)日：2017-04-12
申请号：EP15731175.4
申请日：2015-06-05
发明人： KRIS, Bryan
CPC分类号： G06F13/385 , G06F1/22 , G06F13/287 , G06F15/76
摘要： An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores.
摘要翻译： 嵌入式设备具有多个处理器核心，每个处理器核心具有多个外围设备，其中每个外围设备可以具有输出，具有多个可分配外部引脚的外壳以及用于每个处理核心的多个外围引脚选择模块， 其中每个外围引脚选择模块被配置为可编程以将可分配的外部引脚分配给所述处理器核心之一的所述多个外围设备之一。
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4.发明公开
公开(公告)号：EP1605334A3
公开(公告)日：2012-02-15
申请号：EP05102655.7
申请日：2005-04-04
发明人： Merk, Dieter
IPC分类号： G06F1/22
CPC分类号： G01R31/31701 , G01R31/3172 , G06F1/22
摘要： An interface circuit for a single logic input pin of an electronic system, comprising a decoder 10 for converting a pulse coded signal applied to said pin to a sequence of logic low and logic high values, and a state machine 12 responsive to said sequence of logic values to switch the electronic system between different modes of operation.
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5.发明授权Dynamically configurable debug port for concurrent support of debug functions from multiple data processing cores 有权与同时使用多个处理器内核的误差校正的动态配置的调试接口
公开(公告)号：EP1130501B1
公开(公告)日：2009-07-15
申请号：EP01000035.4
申请日：2001-03-02
发明人： Swoboda, Gary L. , Deao, Douglas E.
IPC分类号： G06F1/22 , G01R31/3185 , G06F11/34
CPC分类号： G06F11/261 , G01R31/31705 , G01R31/318505 , G06F1/22 , G06F11/2733 , G06F11/3466
摘要： An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.
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6.发明公开HALBLEITERKÖRPER, SCHALTUNGSANORDNUNG MIT DEM HALBLEITERKÖRPER UND VERFAHREN 审中-公开半导体主体，具有半导体主体与方法的电路
公开(公告)号：EP1964267A1
公开(公告)日：2008-09-03
申请号：EP06818605.5
申请日：2006-11-16
IPC分类号： H03K19/173 , G06F1/22
CPC分类号： G06F1/22 , H03K19/1732
摘要： An input circuit arrangement (1) has an input (2), a comparator (30) and an evaluation circuit (50). The input (2) is designed for being coupled to a first connection (101) of an impedance (100) and for supplying an input signal (ES). The comparator (30) is connected to the input (2) of the input circuit arrangement (1) and is designed to output an activation signal (S1) at an output (31) as a function of a comparison of the input signal (ES) with a threshold value (SW1) which can be set. Furthermore, the evaluation circuit (50) is connected to the input (2) of the input circuit arrangement (1) and, in order to activate it, to the output (31) of the comparator (30) and is designed to evaluate the value of the impedance (100) which can be connected.
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7.发明公开CIRCUITS AND METHODS FOR IMPLEMENTING MODE SELECTION IN MULTIPLE-MODE INTEGRATED CIRCUITS 审中-公开CIRCUITS AND METHOD FOR模式选择为一体的多CMOS电路的实现
公开(公告)号：EP1828868A2
公开(公告)日：2007-09-05
申请号：EP05851883.8
申请日：2005-11-16
申请人： Cirrus Logic, Inc.
发明人： NANDA, Kartik
IPC分类号： G06F1/22
摘要： Mode selection circuitry selects one a plurality of plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.
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公开(公告)号：EP1086466A1
公开(公告)日：2001-03-28
申请号：EP00917817.9
申请日：2000-03-09
发明人： WOJEWODA, Igor , TRIECE, Joseph, W.
CPC分类号： G11C16/225 , G06F9/24 , G06F9/30101 , G11C16/22
摘要： A microcontroller having a memory programmable in user mode. The microcontroller contains circuitry for detecting whether a programming level voltage has been activated. Also included is a Longwrite enable register containing an enable bit for enabling/disabling programming of the memory. When the register contains the bit indicating programming as enabled, and the programming level voltage is detected, the microcontroller allows the program memory to be programmed. The programming can take place in user mode. The programming level voltage signal is also used to detect whether to enter into a test mode. Programming of the program memory is also possible in the test mode. The invention is also directed to a method for operating a microcontroller for controlling programming of the program memory. The microcontroller according to the invention allows increased functionality by detecting whether to enter the test mode without the requirement of a test mode select input signal.
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公开(公告)号：EP4064001A1
公开(公告)日：2022-09-28
申请号：EP22162915.7
申请日：2022-03-18
摘要： A processing system (10a) is described. The processing system comprises a microprocessor, a reset circuit (116a), a non-volatile memory having stored configuration data, a plurality of configuration data clients (112) and a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data to the configuration data clients (112). In response to switching on the processing system (10a), the processing system (10a) executes a reset phase (DR), a configuration phase (CP1) and a software runtime phase (SW).
In particular, the processing system (10a) comprises a first reset terminal (RPa) having associated a first circuitry (30a, 32a) and a second reset terminal (RPb) having associated a first circuitry (30a, 32a), wherein the first circuitry (30a, 32a) and the second circuitry (30b, 32b) have associated at least one configuration data client (112a, 112b), and wherein the configuration data comprise first mode configuration data (MCDa) for the first terminal (RPa) and second mode configuration data (MCDb) for the second terminal (RPb).
During the reset phase (DR) and the configuration phase (CP1) the first circuitry (30a, 32a) activates a strong pull-down resistance, and the second circuitry (30b, 32b) activate a weak pull-down resistance. Conversely, once the configuration phase is completed, and in particular during the software runtime phase (SW), the first circuitry (30a, 32a) may activate a weak pull-down resistance, e.g., for implementing a bi-direction reset terminal, or a weak pull-up resistance, e.g., for implementing a reset output terminal. Conversely, the second circuitry (30b, 32b) may activate a weak or strong pull-up resistance, e.g., for implementing a reset output terminal, or maintain activated the weak pull-down resistance, e.g., for implementing a reset input terminal.-
公开(公告)号：EP3602234A2
公开(公告)日：2020-02-05
申请号：EP18715864.7
申请日：2018-03-15
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