-
1.发明授权
公开(公告)号：EP0868693B1
公开(公告)日：2003-05-14
申请号：EP96944435.5
申请日：1996-12-19
IPC分类号： G06F11/20
CPC分类号： G11C29/80 , G11C29/808
摘要： A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.
-
2.发明公开
公开(公告)号：EP0868693A1
公开(公告)日：1998-10-07
申请号：EP96944435.0
申请日：1996-12-19
CPC分类号： G11C29/80 , G11C29/808
摘要： A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.
-
搜索结果
2 条记录 (耗时 0.009 秒)
