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1.发明公开
公开(公告)号：EP0868693A1
公开(公告)日：1998-10-07
申请号：EP96944435.0
申请日：1996-12-19
CPC分类号： G11C29/80 , G11C29/808
摘要： A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.
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2.发明公开
公开(公告)号：EP1476877A1
公开(公告)日：2004-11-17
申请号：EP03742713.5
申请日：2003-02-10
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2013/0054 , G11C2013/009 , G11C2213/79
摘要： A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).
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3.发明授权
公开(公告)号：EP1476877B1
公开(公告)日：2008-05-21
申请号：EP03742713.5
申请日：2003-02-10
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2013/0054 , G11C2013/009 , G11C2213/79
摘要： A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).
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4.发明授权
公开(公告)号：EP0868693B1
公开(公告)日：2003-05-14
申请号：EP96944435.5
申请日：1996-12-19
IPC分类号： G06F11/20
CPC分类号： G11C29/80 , G11C29/808
摘要： A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.
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5.发明授权DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUIT DICE IN AN INTEGRATED CIRCUIT MODULE 失效方法和设备测试的集成电路芯片的集成化的电路模块
公开(公告)号：EP0928486B1
公开(公告)日：2001-11-14
申请号：EP97938416.1
申请日：1997-08-20
IPC分类号： G11C29/00 , G06F11/267
CPC分类号： H01L22/22 , G01R31/2884 , G11C29/46 , G11C29/785 , G11C29/80 , G11C29/808 , H01L2224/48091 , H04J2203/0062 , H01L2924/00014
摘要： An IC module (20), such as a Multi-Chip Module (MCM), includes multiple IC (12) dice each having a test mode enable bond pad (30), such as an output enable pad. A fuse incorporated into the MCM's substrate connects each dice's test mode enable pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable pads to one of the MCM's reference voltage pins. By applying a supply voltage to the test mode enable pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a reference voltage applied to the test mode enable pads through the reference voltage pins and the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing, includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the re-tested dice, and evaluating the response signals to confirm all repairs.
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6.发明公开DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUIT DICE IN AN INTEGRATED CIRCUIT MODULE 失效方法和设备测试的集成电路芯片的集成化的电路模块
公开(公告)号：EP0928486A1
公开(公告)日：1999-07-14
申请号：EP97938416.0
申请日：1997-08-20
CPC分类号： H01L22/22 , G01R31/2884 , G11C29/46 , G11C29/785 , G11C29/80 , G11C29/808 , H01L2224/48091 , H04J2203/0062 , H01L2924/00014
摘要： An IC module (20), such as a Multi-Chip Module (MCM), includes multiple IC (12) dice each having a test mode enable bond pad (30), such as an output enable pad. A fuse incorporated into the MCM's substrate connects each dice's test mode enable pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable pads to one of the MCM's reference voltage pins. By applying a supply voltage to the test mode enable pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a reference voltage applied to the test mode enable pads through the reference voltage pins and the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing, includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the re-tested dice, and evaluating the response signals to confirm all repairs.
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