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公开(公告)号：EP0155829B1
公开(公告)日：1991-04-24
申请号：EP85301816.6
申请日：1985-03-15
CPC分类号： G11C29/787 , G11C8/08
摘要： A semiconductor memory device comprises a plurality of row decoder circuits connected with word lines for selecting memory cells. The row decoder circuits include normal row decoder circuits and spare row decoder circuits which can be selected in place of a normal row decoder circuit in case where a fault occurs in a memory cell selected by a word line connected to the normal row decoder circuit. An &upbar& R signal (precharge signal) is applied to an output line (12) of a normal row decoder circuit through a precharge bus (31). A link element (11p) is inserted in the precharge bus (31). The link element (11p) is an element which can be melted by a laser beam, whereby the normal row decoder circuit associated is maintained in a non-selective state. A clamp circuit (14) is also connected to the output line (12). The clamp circuit (14) is a circuit for maintaining the output line (12) at a prescribed low level when the link element (11p) is melted and the associated decoder circuit is brought into a non-selective state.
摘要翻译： 半导体存储器件包括多个与字线连接的行译码器电路，用于选择存储单元。 行解码器电路包括正常行解码器电路和备用行解码器电路，在由与正常行解码器电路连接的字线选择的存储器单元中发生故障的情况下，可以选择正常行解码器电路来代替正常行解码器电路。 一个＆upbar＆R信号（预充电信号）通过一个预充总线（31）加到一个普通行译码器电路的输出线（12）上。 链接元件（11p）插入预充总线（31）中。 链接元件（11p）是可以通过激光束熔化的元件，由此相关的普通行解码器电路保持在非选择状态。 钳位电路（14）也连接到输出线（12）。 钳位电路（14）是用于当链路元件（11p）熔化并且相关的解码器电路进入非选择状态时将输出线路（12）保持在规定的低电平的电路。
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公开(公告)号：EP0461788A3
公开(公告)日：1992-08-19
申请号：EP91304973.0
申请日：1991-05-31
摘要： In an active mode, a transistor 61 or 63 is turned on, so that a reference voltage generator circuit 1 and an internal voltage correcting circuit 2 are activated. Consequently, an internal voltage V INT which is stepped down is applied to an internal main circuit 7. Conversely, in a standby mode, a transistor 61 or 63 is turned off, so that the reference voltage generator circuit 1 and the internal voltage correcting circuit 2 are inactivated. Consequently, the current does not flow in the reference voltage generator circuit 1 and the internal voltage correcting circuit 2, resulting in reduction of a consumption power. Simultaneously, a transistor 62 or 64 is turned on, so that a source voltage Ext.Vcc is directly applied to the internal main circuit 7 through the transistor 62 or 23. Thereby, operation conditions of logic circuits in the internal main circuit 7 are maintained.
摘要翻译： 在有源模式下，晶体管61或63导通，使得参考电压发生器电路1和内部电压校正电路2被激活。 因此，降压的内部电压VINT被施加到内部主电路7.相反，在待机模式中，晶体管61或63被截止，使得参考电压发生器电路1和内部电压校正电路2 被灭活。 因此，电流不会在参考电压发生电路1和内部电压校正电路2中流动，导致消耗功率的降低。 同时，晶体管62或64导通，使得源极电压Ext.Vcc通过晶体管62或23直接施加到内部主电路7.由此，内部主电路7中的逻辑电路的操作条件被保持 。
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公开(公告)号：EP0461788A2
公开(公告)日：1991-12-18
申请号：EP91304973.0
申请日：1991-05-31
摘要： In an active mode, a transistor 61 or 63 is turned on, so that a reference voltage generator circuit 1 and an internal voltage correcting circuit 2 are activated. Consequently, an internal voltage V INT which is stepped down is applied to an internal main circuit 7. Conversely, in a standby mode, a transistor 61 or 63 is turned off, so that the reference voltage generator circuit 1 and the internal voltage correcting circuit 2 are inactivated. Consequently, the current does not flow in the reference voltage generator circuit 1 and the internal voltage correcting circuit 2, resulting in reduction of a consumption power. Simultaneously, a transistor 62 or 64 is turned on, so that a source voltage Ext.Vcc is directly applied to the internal main circuit 7 through the transistor 62 or 23. Thereby, operation conditions of logic circuits in the internal main circuit 7 are maintained.
摘要翻译： 在有源模式下，晶体管61或63导通，使得参考电压发生器电路1和内部电压校正电路2被激活。 因此，降压的内部电压VINT被施加到内部主电路7.相反，在待机模式中，晶体管61或63被截止，使得参考电压发生器电路1和内部电压校正电路2 被灭活。 因此，电流不会在参考电压发生电路1和内部电压校正电路2中流动，导致消耗功率的降低。 同时，晶体管62或64导通，使得源极电压Ext.Vcc通过晶体管62或23直接施加到内部主电路7.由此，内部主电路7中的逻辑电路的操作条件被保持 。
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公开(公告)号：EP0155829A3
公开(公告)日：1987-09-30
申请号：EP85301816
申请日：1985-03-15
CPC分类号： G11C29/787 , G11C8/08
摘要： A semiconductor memory device comprises a plurality of row decoder circuits connected with word lines for selecting memory cells. The row decoder circuits include normal row decoder circuits and spare row decoder circuits which can be selected in place of a normal row decoder circuit in case where a fault occurs in a memory cell selected by a word line connected to the normal row decoder circuit. An RAS signal (precharge signal) is applied to an output line (12) of a normal row decoder circuit through a precharge bus (31). A link element (11 p) is inserted in the precharge bus (31). The link element (11p) is an element which can be melted by a laser beam, whereby the normal row decoder circuit associated is maintained in a non-selective state. A clamp circuit (14) is also connected to the output line (12). The clamp circuit (14) is a circuit for maintaining the output line (12) at a prescribed low level when the link element (11p) is melted and the associated decoder circuit is brought into a non-selective state.
摘要翻译： 半导体存储器件包括多个与字线连接的行译码器电路，用于选择存储单元。 行解码器电路包括正常行解码器电路和备用行解码器电路，在由与正常行解码器电路连接的字线选择的存储器单元中发生故障的情况下，可以选择正常行解码器电路来代替正常行解码器电路。 通过预充总线（31）将RAS信号（预充电信号）施加到正常行译码器电路的输出线（12）。 链接元件（11p）插入预充电总线（31）中。 链接元件（11p）是可以通过激光束熔化的元件，由此相关的普通行解码器电路保持在非选择状态。 钳位电路（14）也连接到输出线（12）。 钳位电路（14）是用于当链路元件（11p）熔化并且相关的解码器电路进入非选择状态时将输出线路（12）保持在规定的低电平的电路。
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公开(公告)号：EP0155829A2
公开(公告)日：1985-09-25
申请号：EP85301816.6
申请日：1985-03-15
CPC分类号： G11C29/787 , G11C8/08
摘要： A semiconductor memory device comprises a plurality of row decoder circuits connected with word lines for selecting memory cells. The row decoder circuits include normal row decoder circuits and spare row decoder circuits which can be selected in place of a normal row decoder circuit in case where a fault occurs in a memory cell selected by a word line connected to the normal row decoder circuit. An RAS signal (precharge signal) is applied to an output line (12) of a normal row decoder circuit through a precharge bus (31). A link element (11 p) is inserted in the precharge bus (31). The link element (11p) is an element which can be melted by a laser beam, whereby the normal row decoder circuit associated is maintained in a non-selective state. A clamp circuit (14) is also connected to the output line (12). The clamp circuit (14) is a circuit for maintaining the output line (12) at a prescribed low level when the link element (11p) is melted and the associated decoder circuit is brought into a non-selective state.
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