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公开(公告)号：EP0509492A1
公开(公告)日：1992-10-21
申请号：EP92106555.3
申请日：1992-04-15
CPC分类号： H04N5/361 , H04N5/3694 , H04N5/378
摘要： In each of corresponding image sensor chips arranged in a line and cascaded with each other to form an image sensor, a dummy photocell (16) which is configured similarly to the photocells (1-1 to 1-N) is provided, having its window is shielded from light. A dummy select switch (17) which selectively makes connection of the dummy photocell (16) with a signal line (3) on which the image signals from the photocells (1-1 to 1-N) are output. The dummy select switch (17) is kept closed upon completion of the drive period of the photocells. This occurs only at the last image sensor chip in the image sensor, so that the output of the dummy photocell (16) is used as a reference for the dark output during the blanking period. In another aspect of the invention, a switch (33) is provided within the chip to shunt the image signal output terminal (11) and the ground responsive to the clock pulse thereby to remove the remaining electric charge from the capacitor (28) provided outside the chips to integrate the output of the image sensor.
摘要翻译： 在布置成一行并且彼此级联以形成图像传感器的每个相应图像传感器芯片中，设置与光电管（1-1至1-N）类似的虚拟光电管（16），其具有窗口 被遮光。 虚拟选择开关（17），其选择性地使虚拟光电池（16）与其上输出来自光电管（1-1至1-N）的图像信号的信号线（3）连接。 虚拟选择开关（17）在光电池的驱动周期完成时保持关闭。 这仅发生在图像传感器中的最后图像传感器芯片处，使得在消隐期间将伪光电管（16）的输出用作暗输出的参考。 在本发明的另一方面中，开关（33）设置在芯片内以分流图像信号输出端（11）和响应于时钟脉冲的地，从而从外部提供的电容器（28）中去除剩余的电荷 芯片集成图像传感器的输出。
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公开(公告)号：EP0509492B1
公开(公告)日：1996-07-10
申请号：EP92106555.3
申请日：1992-04-15
CPC分类号： H04N5/361 , H04N5/3694 , H04N5/378
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3.发明公开Image signal processing apparatus with clock generation for image sensor 失效Bildsignalverarbeitungsvorrichtung mit TakterzeugungfürBildsensor
公开(公告)号：EP1282306A1
公开(公告)日：2003-02-05
申请号：EP02024958.7
申请日：1996-01-18
IPC分类号： H04N5/335
CPC分类号： H04N5/335
摘要： An image signal processing apparatus is provided comprising an image sensor (1) for outputting image data, a sample hold circuit (2) for holding the image data output. The sample hold circuit outputs an analog signal to an AD converter (3) for converting the analog signal to a digital signal. A system clock generator (6a) generates a first clock signal (φ1), while a timing generator (4) controls the hold timing of the sample hold circuit (2) according to the first clock (φ1). A second system clock generator (6b) generates a second system clock signal (φ2) having a different phase from the phase of the first clock signal (φ1). An AD conversion clock generator (5) controls the conversion timing of AD converter (3) according to the second clock (φ2). Since two different clocks are used, the hold timing does not overlap with a conversion timing. Therefore, the reading of the image data becomes stable and misreading can be reduced, where the quality of an image is improved.
摘要翻译： 提供一种图像信号处理装置，包括用于输出图像数据的图像传感器（1），用于保持图像数据输出的采样保持电路（2）。 采样保持电路将模拟信号输出到AD转换器（3），用于将模拟信号转换为数字信号。 系统时钟发生器（6a）产生第一时钟信号（phi 1），而定时发生器（4）根据第一时钟（phi 1）控制采样保持电路（2）的保持定时。 第二系统时钟发生器（6b）产生具有与第一时钟信号（phi 1）的相位不同的相位的第二系统时钟信号（phi2）。 AD转换时钟发生器（5）根据第二时钟（phi 2）控制AD转换器（3）的转换定时。 由于使用了两个不同的时钟，所以保持定时与转换时序不重叠。 因此，图像数据的读取变得稳定，可以降低图像质量的改善。
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