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    DEVICE FOR DETECTING FAILURE IN DRIVING POWER SUPPLY FOR ELEVATOR, AND METHOD FOR DETECTING FAILURE IN DRIVING POWER SUPPLY FOR ELEVATOR
    6.
    发明公开
    DEVICE FOR DETECTING FAILURE IN DRIVING POWER SUPPLY FOR ELEVATOR, AND METHOD FOR DETECTING FAILURE IN DRIVING POWER SUPPLY FOR ELEVATOR 有权
    设备驱动动力提供电梯和方法的一个故障，以便检测驱动动力提供升降机故障的检测

    公开(公告)号：EP1749783A4

    公开(公告)日：2012-06-06

    申请号：EP04745536

    申请日：2004-05-27

    申请人： MITSUBISHI ELECTRIC CORP

    发明人： MATSUOKA TATSUO

    IPC分类号： B66B5/00 ,  B66B5/02

    CPC分类号： B66B5/0031

    摘要： In a feeder circuit for operating a safety device of an elevator, a charging capacitor for actuating an actuator through discharge is employed. A failure detecting device for detecting the presence or absence of a capacitance shortage of a charging capacitor is also electrically connected to the feeder circuit. The failure detecting device has a memory in which a lower limit and upper limit of a charging time at the time when the charging capacitor is in normal operation are stored, and a CPU which is capable of measuring the charging time of the charging capacitor and detects whether or not the charging time is between the lower limit and the upper limit. When the charging time is between the lower limit and the upper limit, the CPU determines that there is no capacitance shortage of the charging capacitor.

    SYSTEM FOR ELEVATOR ELECTRONIC SAFETY DEVICE
    9.
    发明公开
    SYSTEM FOR ELEVATOR ELECTRONIC SAFETY DEVICE 审中-公开
    SYSTEM FOR ELECTRONIC电梯安全装置

    公开(公告)号：EP1764700A4

    公开(公告)日：2009-08-26

    申请号：EP04746541

    申请日：2004-06-22

    申请人： MITSUBISHI ELECTRIC CORP

    发明人： MATSUOKA TATSUO

    IPC分类号： G06F12/16 ,  B66B1/34 ,  B66B3/00 ,  G06F11/16 ,  G06F11/30 ,  G11C29/00

    CPC分类号： B66B1/34 ,  G06F11/167 ,  G11C29/02 ,  G11C29/022 ,  G11C29/74

    摘要： A system for elevator electronic safety device, wherein not only an abnormal-state check of memory data but also an abnormal-state check of address and data buses are performed, thereby enhancing the reliability of abnormal-state check. A hardware circuit (3) and software processings (2a,2b) are used, in addition to a memory data abnormal-state check circuit (1), to periodically execute the check of address (BA) and data (BD) buses. A CPU (2) is caused to periodically output/receive designated data and periodically output designated addresses for checking both cases of '0' and '1' for each of all the bit signals used at least for a memory system with respect to the address (BA) and data (BD) buses.