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11 条记录 (耗时 0.015 秒)

    Instruction register sequence decoder for microprogrammed data processor and method
    2.
    发明公开
    Instruction register sequence decoder for microprogrammed data processor and method 失效
    微处理数据处理器和方法的指令寄存器序列解码器

    公开(公告)号：EP0019392A3

    公开(公告)日：1981-06-10

    申请号：EP80301418

    申请日：1980-04-30

    申请人： MOTOROLA, INC.

    发明人： Tredennick, Harry Leslie ,  Gunter, Thomas Glen

    IPC分类号： G06F09/26

    CPC分类号： G06F9/30094 ,  G06F9/262 ,  G06F9/264 ,  G06F9/268 ,  G06F9/30 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/30167

    摘要： A data processor using microprogrammed control to execute a plurality of macroinstructions and including an instruction register (10) for storing a macroinstruction, received from a program memory, a control store including a micro control store (18) and a nano control store (20) and for storing a plurality of microinstruction routines, each including one or more microinstructions for controlling operations performed by the data processor, and each of the microinstruction routines being associated with a corresponding starting address and an instruction register sequence decoder (14) coupled to an address selection block (16) which is coupled via a line (17) to the control store (18, 20), the decoder (14) being responsive to the macroinstruction stored by the Instruction register (10) for providing a plurality of starting addresses associated with the stored macroinstruction, the decoder (14) effectively causing the data processor to perform each of the microinstruction routines associated with the starting addresses provided by the decoder (14) in order to execute the macroinstruction stored in the instruction register (10).

    Instruction register sequence decoder for microprogrammed data processor and method
    4.
    发明公开
    Instruction register sequence decoder for microprogrammed data processor and method 失效
    指令码寄存器操作顺序为一个微程序的数据处理系统和方法的解码电路。

    公开(公告)号：EP0019392A2

    公开(公告)日：1980-11-26

    申请号：EP80301418.2

    申请日：1980-04-30

    申请人： MOTOROLA, INC.

    发明人： Tredennick, Harry Leslie ,  Gunter, Thomas Glen

    IPC分类号： G06F9/26

    CPC分类号： G06F9/30094 ,  G06F9/262 ,  G06F9/264 ,  G06F9/268 ,  G06F9/30 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/30167

    摘要： A data processor using microprogrammed control to execute a plurality of macroinstructions and including an instruction register (10) for storing a macroinstruction, received from a program memory, a control store including a micro control store (18) and a nano control store (20) and for storing a plurality of microinstruction routines, each including one or more microinstructions for controlling operations performed by the data processor, and each of the microinstruction routines being associated with a corresponding starting address and an instruction register sequence decoder (14) coupled to an address selection block (16) which is coupled via a line (17) to the control store (18, 20), the decoder (14) being responsive to the macroinstruction stored by the Instruction register (10) for providing a plurality of starting addresses associated with the stored macroinstruction, the decoder (14) effectively causing the data processor to perform each of the microinstruction routines associated with the starting addresses provided by the decoder (14) in order to execute the macroinstruction stored in the instruction register (10).

    Alu and condition code control unit for data processor
    9.
    发明公开
    Alu and condition code control unit for data processor 失效
    算术逻辑单元和单元，用于存储在处理单元的条件指令。

    公开(公告)号：EP0221191A1

    公开(公告)日：1987-05-13

    申请号：EP84103253.5

    申请日：1980-04-30

    申请人： MOTOROLA, INC.

    发明人： Tredennick, Harry Leslie ,  Gunter, Thomas Glen

    IPC分类号： G06F9/26

    CPC分类号： G06F9/30094 ,  G06F9/262 ,  G06F9/264 ,  G06F9/268 ,  G06F9/30 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/30167

    摘要： A data processor which is adapted for microprogrammed operation has a control store includes an ALU and condition code control unit for controlling operations performed by an arithmetic-logic unit within the execution unit of the data processor and for controlling the setting of the condition code bits in a status register. The ALU and condition code control unit is arranged in a row and column format. A decoder coupled to a macroinstruction register selects a row which is selected over an entire period that is required to execute macroinstruction. The row corresponds to a set of operations and condition code settings associated with a particular macroinstruction. The control store output provides information for selecting the proper column during each microcycle used to execute the macroinstruction. ALU function control signals and the condition code control signals are selected simultaneously according to the selected row and column.

    摘要翻译： 一种数据处理器，所有这些是angepasst用于编程手术微具有控制存储包括在ALU和条件码控制单元，用于控制数据处理器的执行单元内执行通过算术逻辑单元来执行操作和控制的条件码位的在设置 状态寄存器。 的ALU和条件码控制单元以行和列格式排列。 耦合到一个宏指令寄存器A解码器选择的行被选择到整个期间所有没被执行宏指令必需的。 该行对应一组与特定的宏指令相关的操作和条件码设置的。 控制存贮器输出提供用于用于执行宏指令每个微周期期间选择适当的列的信息。 ALU功能控制信号和条件码的控制信号被选择同时gemäß到选定的行和列。

    Conditional branch unit for microprogrammed data processor
    10.
    发明公开
    Conditional branch unit for microprogrammed data processor 失效
    Bedingte Verzweigungseinheitfüreine mikroprogrammierte Datenverarbeitungsanlage。

    公开(公告)号：EP0211962A1

    公开(公告)日：1987-03-04

    申请号：EP84103272.5

    申请日：1980-04-30

    申请人： MOTOROLA, INC.

    发明人： Tredennick, Harry Leslie ,  Gunter, Thomas Glen

    IPC分类号： G06F9/26 ,  G06F9/32

    CPC分类号： G06F9/30094 ,  G06F9/262 ,  G06F9/264 ,  G06F9/268 ,  G06F9/30 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/30167

    摘要： A data processor having a microprogrammed control store and including a conditional branch control unit for receiving selection bits output by the control store, selection bits from an instruction register, and conditional signals for generating a two-bit result which, when added to a base address, can specify one of two, three, or four branch destinations in the control store. The selection bits output by the control store determine whether the combination of conditional signals upon which the branch is dependent is selected by the control store or is selected directly by a bit field in the macroinstruction. Also, one of the selection bits output by the control store is used to select one of two possible output codes for the two-bit result associated with a particular branch destination. The latter feature allows for two conditional branch points in the control store to test for the same condition and to select the same destination when the tested condition is of one logic state while selecting different destinations when the tested condition is of the opposite logic state.

    摘要翻译： 具有微程序控制存储的数据处理器，包括用于接收由控制存储器输出的选择位的条件转移控制单元，来自指令寄存器的选择位，以及用于产生两位结果的条件信号，当被加到基址 ，可以在控制存储中指定两个，三个或四个分支目的地之一。 由控制存储器输出的选择位确定控制存储器是否选择分支依赖的条件信号的组合，或者由宏指令中的位字段直接选择。 此外，由控制存储器输出的选择位之一用于选择与特定分支目的地相关联的两位结果的两个可能输出代码之一。 后一个特征允许控制存储器中的两个条件分支点测试相同的条件，并且当测试条件是一个逻辑状态时选择相同的目的地，而当测试条件是相反的逻辑状态时，选择不同的目的地。