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公开(公告)号:EP2158543B1
公开(公告)日:2013-05-15
申请号:EP08770624.8
申请日:2008-06-11
IPC分类号: G11C11/56
CPC分类号: G11C16/12 , G11C7/16 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C29/021 , G11C29/028 , G11C2211/5641
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公开(公告)号:EP2158543A1
公开(公告)日:2010-03-03
申请号:EP08770624.8
申请日:2008-06-11
IPC分类号: G06F12/00
CPC分类号: G11C16/12 , G11C7/16 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C29/021 , G11C29/028 , G11C2211/5641
摘要: Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability.
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