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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DEFINING DATA IN SEMICONDUCTOR MEMORY DEVICE
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DEFINING DATA IN SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：EP3483888A2

    公开(公告)日：2019-05-15

    申请号：EP18192298.0

    申请日：2018-09-03

    申请人： Renesas Electronics Corporation

    发明人： NAGASE, Hirokazu

    IPC分类号： G11C11/56 ,  G11C16/34

    CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/32 ,  G11C16/349 ,  G11C2211/5641 ,  G11C2211/5644

    摘要： To provide a semiconductor memory device capable of storing multi-value data while suppressing an increase in the threshold voltage set for a memory cell. The semiconductor memory device comprises a plurality of memory cells and a memory controller. The memory cells have a plurality of memory cell pairs, each having a first memory cell and a second memory cell, and the memory controller is configured to set the first memory cell to at least one threshold voltage, and to set the second memory cell to each threshold voltage of a plurality of threshold voltages. The memory controller is configured to read data stored in each memory cell pair by using differences between the threshold voltages of the corresponding second memory cell and the threshold voltage of the corresponding first memory cell.

    THREE-DIMENSIONAL VERTICAL NOR FLASH THIN FILM TRANSISTOR STRINGS
    6.
    发明公开
    THREE-DIMENSIONAL VERTICAL NOR FLASH THIN FILM TRANSISTOR STRINGS 审中-公开

    公开(公告)号：EP3381036A1

    公开(公告)日：2018-10-03

    申请号：EP16869049.3

    申请日：2016-11-04

    申请人： Sunrise Memory Corporation

    发明人： HARARI, Eli

    IPC分类号： G11C7/18 ,  H01L21/8242 ,  G11C11/409

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0416 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11582

    摘要： A memory structure, includes a plurality of thin film transistors associated with each of a plurality of active columns, which are organized into one or more vertical NOR strings comprising (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form the plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions.

    NON-VOLATILE MEMORY AND METHOD WITH ACCELERATED POST-WRITE READ USING COMBINED VERIFICATION OF MULTIPLE PAGES
    8.
    发明授权
    NON-VOLATILE MEMORY AND METHOD WITH ACCELERATED POST-WRITE READ USING COMBINED VERIFICATION OF MULTIPLE PAGES 有权

    公开(公告)号：EP2737486B1

    公开(公告)日：2018-06-06

    申请号：EP12743320.9

    申请日：2012-07-25

    申请人： SanDisk Technologies LLC

    发明人： SHARON, Eran

    IPC分类号： G11C11/56 ,  G06F11/10

    CPC分类号： G11C11/5642 ,  G06F11/1048

    摘要： A post-write read operation, using a combined verification of multiple pages of data, is presented. In a simultaneous verification of multiple pages in a block, the controller evaluates a combined function of the multiple pages, instead of evaluating each page separately. In one exemplary embodiment, the combined function is formed by XORing the pages together. Such a combined verification of multiple pages based on the read data can significantly reduce the controller involvement, lowering the required bus and ECC bandwidth for a post-write read and hence allow efficient post-write reads when the number of dies is large.

    APPARATUSES AND METHODS FOR SEGMENTED SGS LINES
    9.
    发明公开
    APPARATUSES AND METHODS FOR SEGMENTED SGS LINES 审中-公开

    公开(公告)号：EP3210209A4

    公开(公告)日：2018-05-16

    申请号：EP15852706

    申请日：2015-10-07

    申请人： MICRON TECHNOLOGY INC

    发明人： PAN FENG ,  PARK JAEKWAN ,  GHODSI RAMIN

    IPC分类号： G11C8/12 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

    CPC分类号： G11C16/0483 ,  G11C8/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    摘要： Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.