Analogue/digital delay locked loop
    1.
    发明授权
    Analogue/digital delay locked loop 有权
    模拟/ DIGITALES DLL

    公开(公告)号:EP2251980B1

    公开(公告)日:2012-05-23

    申请号:EP10171395.6

    申请日:2003-12-29

    IPC分类号: H03L7/081 H03L7/10

    摘要: There is disclosed a delay locked loop (300) comprising: a digital delay circuit (302) which enables digital delay elements (400) to provide coarse phase adjustment during initialization in the delay locked loop (300); a counter (308) configured to control the number of the digital delay elements (400) enabled; and an analog delay circuit (304) which provides, after coarse phase adjustment is completed, a fine phase adjustment in the delay locked loop (300), and wherein the analog delay circuit (304) employs a variable control signal during the fine phase adjustment.

    Analogue/digital delay locked loop
    2.
    发明公开
    Analogue/digital delay locked loop 有权
    模拟/数字延迟锁定环路

    公开(公告)号:EP2251980A1

    公开(公告)日:2010-11-17

    申请号:EP10171395.6

    申请日:2003-12-29

    IPC分类号: H03L7/087

    摘要: There is disclosed a delay locked loop (300) comprising: a digital delay circuit (302) which enables digital delay elements (400) to provide coarse phase adjustment during initialization in the delay locked loop (300); a counter (308) configured to control the number of the digital delay elements (400) enabled; and an analog delay circuit (304) which provides, after coarse phase adjustment is completed, a fine phase adjustment in the delay locked loop (300), and wherein the analog delay circuit (304) employs a variable control signal during the fine phase adjustment.

    摘要翻译: 公开了一种延迟锁定环路(300),包括:数字延迟电路(302),其使数字延迟元件(400)能够在延迟锁定环路(300)中的初始化期间提供粗略的相位调整; 计数器(308),被配置为控制启用的数字延迟元件(400)的数量; 以及模拟延迟电路(304),其在粗略的相位调整完成​​之后在延迟锁定环路(300)中提供精细的相位调整,并且其中模拟延迟电路(304)在精细相位调整期间采用可变控制信号 。

    HIGH OUTPUT IMPEDANCE CHARGE PUMP FOR PLL/DLL
    3.
    发明公开
    HIGH OUTPUT IMPEDANCE CHARGE PUMP FOR PLL/DLL 审中-公开
    具有高输出阻抗PLL / DLL电荷泵

    公开(公告)号:EP1692767A1

    公开(公告)日:2006-08-23

    申请号:EP04802287.5

    申请日:2004-12-10

    发明人: Haerle, Dieter

    IPC分类号: H03L7/00 H03L7/08

    CPC分类号: H03L7/0895 H03L7/0812

    摘要: A charge pump for use in a Phase Locked Loop/Delay Locked Loop, comprising a pull-up circuit, a pull-down circuit, and an operational amplifier. The charge pump is designed to minimize the static phase error associated with the operation of the pull-up and pull down circuits. The use of the operational amplifier also mitigates the effects of low power supply voltage.

    Analogue/digital delay locked loop
    4.
    发明公开
    Analogue/digital delay locked loop 审中-公开
    模拟/数字DLL

    公开(公告)号:EP2264902A1

    公开(公告)日:2010-12-22

    申请号:EP10183259.0

    申请日:2003-12-29

    IPC分类号: H03L7/087

    摘要: There is disclosed a delay locked loop (300) comprising: a digital delay circuit (302) which enables digital delay elements (400) to provide coarse phase adjustment during initialization in the delay locked loop (300); a counter (308) configured to control the number of the digital delay elements (400) enabled; and an analog delay circuit (304) which provides, after coarse phase adjustment is completed, a fine phase adjustment in the delay locked loop (300), and wherein the analog delay circuit (304) employs a variable control signal during the fine phase adjustment.

    摘要翻译: 公开了一种延迟锁定环路(300),包括:数字延迟电路(302),其使数字延迟元件(400)能够在延迟锁定环路(300)中的初始化期间提供粗略的相位调整; 配置为控制启用的数字延迟元件(400)的数量的计数器(308) 以及模拟延迟电路(304),其在粗调相位调整完成​​之后,在所述延迟锁定环(300)中提供精细相位调整,并且其中所述模拟延迟电路(304)在精细相位调整期间采用可变控制信号 。