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公开(公告)号：EP2267899B1
公开(公告)日：2019-06-12
申请号：EP10004515.2
申请日：2010-04-29
Applicant: Rohde & Schwarz GmbH & Co. KG
Inventor： Dümler, Ulrich
CPC classification number: H03L7/0812 , H03K5/135 , H03K2005/00026 , H03K2005/00058 , H03L7/087 , H03L7/10
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公开(公告)号：EP2183674B1
公开(公告)日：2018-01-24
申请号：EP08772568.5
申请日：2008-07-16
Inventor： KIM, Chulwoo , JUNG, Inhwa
IPC: G06F13/14 , H03L7/08 , H03L7/087 , H03L7/095 , H03L7/099 , H03L7/10 , H04L7/04 , H03L7/089 , G06F13/38 , H04L7/033
CPC classification number: G06F13/385 , H03L7/0807 , H03L7/087 , H03L7/0891 , H03L7/095 , H03L7/099 , H03L7/10 , H04L7/033 , H04L7/044
Abstract: A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.
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3.发明授权A time base generator and method for providing a first clock signal and a second clock signal 有权时基发生器和方法，用于提供第一时钟信号和第二时钟信号
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4.发明公开Simplified dual modulus divider and method of designing a phase locked loop with first and second divider circuits 审中-公开简化双模分频器和方法，用于设计具有第一和第二分频电路锁相环
公开(公告)号：EP2757693A3
公开(公告)日：2015-07-29
申请号：EP14165273.5
申请日：2001-12-17
Applicant: Qualcomm Incorporated
Inventor： Su, David, K. , Yue, Chik, Patrick , Weber, David, J. , Zargari, Masoud
CPC classification number: H03L7/099 , H03K23/667 , H03L7/089 , H03L7/095 , H03L7/10 , H03L7/193 , Y10S331/02
Abstract: The present invention provides a synthesiser having a divide circuit implemented using only a single counter along with a decoder. This allows for a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
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公开(公告)号：EP2647127A1
公开(公告)日：2013-10-09
申请号：EP10860178.2
申请日：2010-12-01
Applicant: Telefonaktiebolaget LM Ericsson (PUBL)
Inventor： WEN, Gan
Abstract: A method and circuit is provided for determining a control voltage of a voltage controlled oscillator with fast frequency lock of a phase-locked loop and which is advantageous to the situation when an ultra-low frequency reference is used. The method and circuit determines a current error between a reference clock signal and a feedback clock signal, and checks if the error is larger than the threshold value which checks if an error sign indicator is set, i.e. the error has switched sign since startup of feedback loop; if the error sign indicator is not set, the circuit determines a divisor, k
n , using the current error, e
n , current control voltage, u
n , previous error e
n-1 , and previous control voltage, u
n-1 ; however, if the error sign indicator is set the circuit determines a divisor, k
n , using stored values for the latest control voltage and error when the error was negative and stored values for the latest control voltage and error when the error was positive; furthermore, the method and circuit determines a control voltage step using the determined error divided by the divisor, k
n , and determines a new control voltage using the current control voltage, u
n , and the determined control voltage step.-
Patent Agency Ranking
公开(公告)号：EP2577669A2
公开(公告)日：2013-04-10
申请号：EP11790247.8
申请日：2011-05-27
Applicant: Intel Corporation
Inventor： MOSALIKANTI, Praveen , KURD, Nasser A. , MOZAK, Christopher P.
CPC classification number: G06F1/324 , G06F1/3296 , H03L7/0802 , H03L7/0812 , H03L7/10 , H03L7/143 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.
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公开(公告)号：EP2003781B1
公开(公告)日：2013-01-23
申请号：EP07739217.3
申请日：2007-03-14
Applicant: NIHON DEMPA KOGYO CO., LTD.
Inventor： KOBATA, Tsukasa , SHIOBARA, Tsuyoshi , AKAIKE, Kazuo , TSUKAMOTO, Nobuo
CPC classification number: H03L7/18 , H03L7/085 , H03L7/091 , H03L7/10 , H03L7/185 , H03L7/187 , H03L2207/06 , H03L2207/12
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公开(公告)号：EP2502349A1
公开(公告)日：2012-09-26
申请号：EP10755231.7
申请日：2010-09-17
Applicant: Aeroflex International Limited
Inventor： THOMAS, Neil Edwin
CPC classification number: H03L7/087 , H03L7/10 , H03L7/185 , H03L7/189 , H03L2207/06 , H03L2207/12
Abstract: A phase locked loop (10) comprising: a tuneable oscillator (12); a mixer-based phase sensitive detector (18) to receive input signals from the tuneable oscillator (12) and a reference signal (20); a cycle slip detector (26) to receive input signals from the tuneable oscillator (12) and the reference signal (20), the cycle slip detector (26) being configured to generate an output signal when two consecutive pulses are present in one of its input signals without an intervening pulse in the other of its input signals; coarse tune signal means (32, 34) to receive the output signal generated by the cycle slip detector; and adding means (24) for adding a signal output by the coarse signal means (32, 34) to a signal output by the phase sensitive detector (18) to control the frequency of the tuneable oscillator (12).
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9.发明公开Delay locked loop including a mechanism for reducing lock time 有权Verzögerungsregelschleifemit Mechanismus zur Reduzierung der Sperrzeit
公开(公告)号：EP2439848A1
公开(公告)日：2012-04-11
申请号：EP11184522.8
申请日：2011-10-10
Applicant: Apple Inc.
Inventor： Trivedi, Pradeep R. , Von Kaenel, Vincent R.
CPC classification number: H03L7/0816 , H03L7/0818 , H03L7/089 , H03L7/10
Abstract: A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in a delay associated with the delay line. The DLL may also include a step size controller that may provide a step size indication corresponding to a first step size in response to detecting the output signal indicating a first change in delay, and to provide a step size indications corresponding to a second step size that is smaller than the first step size in response to detecting the output signal indicating a second change in delay.
Abstract translation: 延迟锁定环（DLL）包括被配置为提供参考时钟的延迟版本作为反馈时钟的延迟线。 该DLL还包括相位检测器，其可以提供指示与延迟线相关联的延迟的变化的输出信号。 DLL还可以包括步长控制器，其可以响应于检测到指示延迟的第一改变的输出信号而提供对应于第一步长的步长指示，并且提供对应于第二步长的步长大小指示 响应于检测到指示延迟的第二改变的输出信号，小于第一步长。
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公开(公告)号：EP2267899A1
公开(公告)日：2010-12-29
申请号：EP10004515.2
申请日：2010-04-29
Applicant: Rohde & Schwarz GmbH & Co. KG
Inventor： Dümler, Ulrich
CPC classification number: H03L7/0812 , H03K5/135 , H03K2005/00026 , H03K2005/00058 , H03L7/087 , H03L7/10
Abstract: Vorrichtung (1) zum Erzeugen einer vorgegebenen Phasenverschiebung zwischen zwei Ausgangssignalen (I,Q) mit einer Verzögerungs-Kette (2) aus mehreren seriell hintereinander angeordneten Verzögerungs-Gliedern (2 1 -2 4 ). Es sind mehrere Phasendetektoren (10 1 -10 4 ) jeweils zum Erfassen der Phasendifferenz zwischen dem Signal am Ausgang eines zugeordneten Verzögerungs-Glieds (2 1 -2 4 ) und einem ersten Referenz-Signal (SR 1 ), das in einer festen Phasenbeziehung zum ersten Ausgangssignal (I) steht, vorhanden. Eine Auswahleinrichtung (11) steht mit den Ausgängen der Phasendetektoren (10 1 -10 4 ) in Verbindung und wählt dasjenige Verzögerungs-Glied (2 1 -2 4 ) aus, an dessen Ausgang die durch den zugeordneten Phasendetektor (10 1 -10 4 ) erfasste Phasendifferenz mit der vorgegebenen Phasenverschiebung in grober Übereinstimmung steht. Eine Schalteinrichtung (12) dient zum Durchschalten des Ausgangs desjenigen Verzögerungs-Gliedes (2 1 -2 4 ), welches von der Auswahleinrichtung (11) ausgewählt wurde, um das zweite Ausgangssignal (Q) zu erzeugen.
Abstract translation: 设备（1）具有由多个串行布置的延迟元件（2-1-2-4）组成的延迟链（2）。 提供多个相位检测器用于检测延迟元件出口处的两个输出信号（I，Q）之间的相位差。 参考信号与输出信号（I）中的一个保持稳定的相位关系。 选择装置与相位检测器的出口保持连接，并选择延迟元件。 开关装置连接由选择装置选择的延迟元件的出口以产生另一个输出信号。
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