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公开(公告)号：EP0545521A3
公开(公告)日：1994-08-24
申请号：EP92307322.5
申请日：1992-08-11
IPC分类号： H01L29/91 , H01L27/06 , H01L21/329 , H01L21/82
CPC分类号： H01L27/0623 , H01L27/0664 , Y10S257/917
摘要： A Schottky diode structure (4) is formed by retrograde diffusing an N⁺ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction. The Schottky diode structure may be formed as part of a BICMOS integrated circuit fabrication process wherein the buried diode layer may be formed at the same time as a buried collector layer of a bipolar transistor structure, the diode NWell may be formed at the same time as an NWell of a CMOS transistor structure and the diode ohmic contact region may be formed at the same time as a collector sink region. In the BICMOS fabrication process the buried collector layer definition mask is also a buried diode layer definition mask, the retro NWell definition mask is also a diode NWell definition mask, the collector sink definition mask is also a diode ohmic contact region definition mask, and the BICMOS contacts definition mask is also a diode junction and ohmic contact definition mask.
摘要翻译： 改进的肖特基二极管结构（4）通过逆向扩散相对较快的扩散原子（优选磷原子）的N +浓度形成，以形成二极管的二极管衬底的局部二极管NWell（6）。 由相对缓慢扩散的N型原子（优选锑原子）形成的埋二极管层（5）位于二极管NWell的下面，并将二极管结（7）电耦合到二极管欧姆接触（9）。 二极管欧姆接触区（31）位于欧姆接触之下，进一步将二极管结耦合到欧姆接触。 优选地，二极管结是铂 - 硅化物结。 改进的肖特基二极管结构可以形成为BICMOS集成电路制造工艺的一部分，其中埋入二极管层可以与双极晶体管结构的掩埋集电极层同时形成，二极管NWell可以同时形成 作为CMOS晶体管结构的NWell，并且二极管欧姆接触区域可以在集电极阱区域的同时形成。 在BICMOS制造工艺中，埋地集电极层定义掩模也是埋地二极管层定义掩模，复古NWell定义掩模也是二极管NWell定义掩模，集电极阱定义掩模也是二极管欧姆接触区域定义掩模，而 BICMOS触点定义掩码也是二极管结和欧姆接触定义掩码。
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2.发明公开NMOS LDD PMOS HALO IC process for CMOS transistors 失效NMOS LDD PMOS HALO IC HerstellungsverfahrenfürCMOS Transistoren。
公开(公告)号：EP0595484A1
公开(公告)日：1994-05-04
申请号：EP93307831.3
申请日：1993-10-01
IPC分类号： H01L21/82 , H01L27/06 , H01L27/092
CPC分类号： H01L21/823807 , H01L27/0623 , H01L27/0927 , H01L29/1045 , H01L29/1083
摘要： A low dose of N type dopant material is introduced in the source and drain regions of CMOS transistors using the polygate POLY and field oxide regions FOX as a self aligned transistor SAT mask and forming a lightly doped N-LDD layer in the source and drain regions of NMOS transistors and a lightly doped halo layer PHLDD in the source and drain regions of PMOS transistors. A PMOS transistor P+S/D definition mask, etch and P type dopant material introduction sequence introduces P+ concentration source and drain regions in the PMOS transistors over the N- halo layer. The P+S/D implant is adjusted for erasing the halo layer along the horizontal interface between the source and drain regions and underlying NWELL but preserving the halo layer at the ends of the channel under the polygate between the source and drain regions of the PMOS transistors. The localized halo PHLDD of N type dopant material at the ends of the channel enhances punch through protection between the source and drain regions of the PMOS transistors by 20% - 30% without substantially increasing parasitic capacitance between the NWELL and source and drain regions. The N+S/D definition mask, etch and N+ dopant material introduction sequence for NMOS transistors retains a portion of the N-LDD layer along the horizontal interface for reducing parasitic capacitance and at the edges of the channel for hot electron protection of the gate oxide of NMOS transistors. The new architecture for source and drain regions of CMOS transistors and new IC fabrications steps provide enhanced punch through protection for PMOS transistors and hot electron protection for NMOS transistors while reducing parasitic capacitance across active areas of the CMOS transistors.
摘要翻译： 使用Polygate POLY和场氧化物区域FOX作为自对准晶体管SAT掩模将低剂量的N型掺杂剂材料引入CMOS晶体管的源极和漏极区域中，并在源极和漏极区域中形成轻掺杂的N-LDD层 的NMOS晶体管和PMOS晶体管的源极和漏极区域中的轻掺杂卤素层PHLDD。 PMOS晶体管P + S / D定义掩模，蚀刻和P型掺杂剂材料引入顺序在N-halo层上引入PMOS晶体管中的P +浓度源极和漏极区。 调整P + S / D植入物以沿着源极和漏极区域和下游NWELL之间的水平界面擦除卤素层，但是在PMOS的源极和漏极区域之间的多晶硅栅极下方的沟道的末端保留晕圈 晶体管。 在沟道端部的N型掺杂剂材料的局部卤化PHLDD增强了PMOS晶体管的源极和漏极区域之间的冲击保护20％-30％，而基本上不增加NWELL与源极和漏极区域之间的寄生电容。 用于NMOS晶体管的N + S / D定义掩模，蚀刻和N +掺杂剂材料引入序列沿着水平界面保留了N-LDD层的一部分，用于减小寄生电容，并在栅极的边缘处保护栅极的热电子保护 NMOS晶体管的氧化物。 CMOS晶体管的源极和漏极区域的新架构以及新的IC制造步骤为PMOS晶体管提供了增强的穿透保护，并为NMOS晶体管提供了热电子保护，同时降低了CMOS晶体管的有源区域的寄生电容。
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3.发明授权Process for fabricating a retrograde nwell cathode Schottky transistor and fabrication process 失效一种用于生产具有回生n阱阴极的肖特基晶体管工艺
公开(公告)号：EP0592084B1
公开(公告)日：1998-01-07
申请号：EP93306385.1
申请日：1993-08-12
IPC分类号： H01L27/07 , H01L21/331
CPC分类号： H01L27/0766
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4.发明公开Integrated circuit fabrication process and structure 失效Herstellungsverfahrenfüreine integrierte Schaltung und Struktur。
公开(公告)号：EP0545363A1
公开(公告)日：1993-06-09
申请号：EP92120493.9
申请日：1992-12-01
IPC分类号： H01L21/329 , H01L21/82 , H01L27/06
CPC分类号： H01L29/66166 , H01L21/823892 , H01L21/8249 , H01L27/0629 , H01L27/0928
摘要： A high definition, high resistance resistor structure is formed in a resistor PWell by shallowly implanting a well-defined resistive region of the resistor PWell with relatively fast-diffusing N type atoms in an N⁻ concentration, and shallowly implanting a well-defined resistor contacts regions with relatively slow-diffusing N type atoms in an N⁺ concentration. The high definition, high resistance resistor structure (2) fabrication steps are integrated into MOS transistor structure fabrication steps without adding any new steps to the process. The resistor PWell is formed at the same time as the MOS transistor structure PWell, the resistive region is implanted at the same time as the low density drain (LDD) regions for the MOS device, and the resistor contacts regions are implanted at the same time as the source and drain regions of the MOS transistor structure. MOS transistor masks are modified to include a resistor PWell definition opening, a resistive region definition opening, resistor contacts regions definition openings, and resistor contacts definition openings.
摘要翻译： 通过以N +浓度相对快速扩散的N型原子浅埋入电阻器PWell的良好限定的电阻区域，在电阻器PWell中形成高清晰度，高电阻电阻器结构，并且浅埋入良好的 具有N +浓度相对缓慢扩散的N型原子的电阻器接触区域。 高清晰度，高电阻电阻结构（2）制造步骤集成到MOS晶体管结构制造步骤中，而不需要为工艺增加任何新的步骤。 电阻器PWell与MOS晶体管结构PWell同时形成，电阻区域与MOS器件的低密度漏极（LDD）区域同时注入，并且电阻器接触区域同时被注入 作为MOS晶体管结构的源极和漏极区域。 MOS晶体管掩模被修改为包括电阻器PWell定义开口，电阻区域定义开口，电阻器触点区域定义开口和电阻器触点定义开口。
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5.发明公开Bipolar transistor structure & BICMOS IC fabrication process 失效Bipolartransistorstruktur和BICMOS IC-Herstellungsverfahren。
公开(公告)号：EP0500233A2
公开(公告)日：1992-08-26
申请号：EP92300994.8
申请日：1992-02-06
CPC分类号： H01L29/0826 , H01L21/74 , H01L21/8249 , H01L27/0623
摘要： A localized subemitter collector region (SEC) is formed in the buried collector layer (BCL) underlying the emitter region (E) and active base region layer (ABL) of a bipolar transistor structure (12). The subemitter collector region (SEC) is implanted with relatively fast diffusing N type atoms distributed in a retrograde concentration upward from the buried collector layer (BCL) into the epitaxial layer (EPI) and preferably up to the active base region layer (ABL) below the emitter region (E). Preferably, phosphorous atoms are implanted in the subemitter collector region to a relatively high N+ concentration. The subemitter collector region (SEC) occupies a horizontal cross section area approximately 10% to 20% of the horizontal cross section area of the buried collector layer. The bipolar NPN transistor structure (12) is incorporated in a BICMOS integrated circuit. In the BICMOS IC fabrication process the NWELL definition and implant mask for the CMOS transistor structure is also a subemitter collector definition and implant mask providing an SEC definition opening for the bipolar transistor structure. The field oxide definition mask with framing field oxide openings (20) for the CMOS transistor structure is also a collector base surface spacer region definition mask with a CBSS defining opening (22) over the bipolar transistor structure.
摘要翻译： 在双极晶体管结构（12）的发射极区域（E）和有源基极区域（ABL）下方的掩埋集电极层（BCL）中形成局部化的子集电极区域（SEC）。 子集电极区域（SEC）以相对较快的扩散N型原子注入，其以逆向集中分布从掩埋集电极层（BCL）向上延伸到外延层（EPI）中，并且优选地至多到下面的有源碱基区域（ABL） 发射极区域（E）。 优选地，将磷原子注入到相当高的N +浓度的子集电极区域中。 子集电极区域（SEC）占据埋藏集电极层的水平横截面面积的约10％至20％的水平横截面积。 双极NPN晶体管结构（12）被并入BICMOS集成电路中。 在BICMOS IC制造工艺中，用于CMOS晶体管结构的NWELL定义和注入掩模也是提供用于双极晶体管结构的SEC定义开口的子传输器集电极定义和注入掩模。 具有用于CMOS晶体管结构的成帧场氧化物开口（20）的场氧化物定义掩模也是在双极晶体管结构上具有CBSS限定开口（22）的集电器基表面间隔区域定义掩模。
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公开(公告)号：EP0545521B1
公开(公告)日：2000-07-19
申请号：EP92307322.5
申请日：1992-08-11
IPC分类号： H01L29/872 , H01L27/06 , H01L21/329
CPC分类号： H01L27/0623 , H01L27/0664 , Y10S257/917
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7.发明公开Retrograde nwell cathode Schottky transistor and fabrication process 失效肖特基晶体管mit retrograderter n-Wannenkathode。
公开(公告)号：EP0592084A1
公开(公告)日：1994-04-13
申请号：EP93306385.1
申请日：1993-08-12
IPC分类号： H01L27/07
CPC分类号： H01L27/0766
摘要： An improved Schottky transistor structure ( 6 ), including a bipolar transistor structure ( 7 ) and a Schottky diode structure ( 8 ), is formed by retrograde diffusing relatively fast diffusing atoms to form a localized retrograde diode well ( 9 ) as the substrate for the Schottky diode structure. An expanded buried collector layer ( 11 ) formed of relatively slow diffusing atoms underlies the base and collector regions of the bipolar transistor structure ( 7 ) and the retrograde diode well ( 9 ). A diode junction ( 10 ) is formed by expanding the base contact of the bipolar transistor structure to include the surface of the retrograde diode well. Preferably, the diode junction is a Platinum-Silicide junction. The improved Schottky transistor structure may be formed as part of a bipolar junction transistor fabrication process or a BICMOS integrated circuit fabrication process wherein the buried diode layer may be formed at the same time as the buried collector layer of the bipolar transistor structure and the retrograde diode well may be formed at the same time as the sub-emitter collector region of the bipolar transistor structure. The buried collector layer definition mask is also a buried diode layer definition mask, the sub-emitter collector region definition mask is also a retrograde diode well definition mask, and the bipolar contacts definition mask is also a diode junction contact definition mask.
摘要翻译： 通过逆向扩散较快的扩散原子形成包括双极晶体管结构（7）和肖特基二极管结构（8）的改进的肖特基晶体管结构（6），以形成局部逆行二极管阱（9）作为 肖特基二极管结构。 由相对慢的扩散原子形成的扩展的掩埋集电极层（11）位于双极晶体管结构（7）和逆向二极管阱（9）的基极和集电极区之下。 二极管结（10）通过使双极晶体管结构的基极接触膨胀以包括逆行二极管阱的表面而形成。 优选地，二极管结是铂 - 硅化物结。 改进的肖特基晶体管结构可以形成为双极结型晶体管制造工艺或BICMOS集成电路制造工艺的一部分，其中埋入二极管层可以与双极晶体管结构的掩埋集电极层和逆向二极管 可以与双极晶体管结构的子发射极集电极区域同时形成阱。 掩埋集电极层定义掩模也是埋地二极管层定义掩模，子发射极集电极区域定义掩模也是逆向二极管阱定义掩模，双极接触定义掩模也是二极管接点定义掩模。
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公开(公告)号：EP0545521A2
公开(公告)日：1993-06-09
申请号：EP92307322.5
申请日：1992-08-11
IPC分类号： H01L29/91 , H01L27/06 , H01L21/329 , H01L21/82
CPC分类号： H01L27/0623 , H01L27/0664 , Y10S257/917
摘要： A Schottky diode structure (4) is formed by retrograde diffusing an N⁺ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction. The Schottky diode structure may be formed as part of a BICMOS integrated circuit fabrication process wherein the buried diode layer may be formed at the same time as a buried collector layer of a bipolar transistor structure, the diode NWell may be formed at the same time as an NWell of a CMOS transistor structure and the diode ohmic contact region may be formed at the same time as a collector sink region. In the BICMOS fabrication process the buried collector layer definition mask is also a buried diode layer definition mask, the retro NWell definition mask is also a diode NWell definition mask, the collector sink definition mask is also a diode ohmic contact region definition mask, and the BICMOS contacts definition mask is also a diode junction and ohmic contact definition mask.
摘要翻译： 改进的肖特基二极管结构（4）通过逆向扩散相对较快的扩散原子（优选磷原子）的N +浓度形成，以形成二极管的二极管衬底的局部二极管NWell（6）。 由相对缓慢扩散的N型原子（优选锑原子）形成的埋二极管层（5）位于二极管NWell的下面，并将二极管结（7）电耦合到二极管欧姆接触（9）。 二极管欧姆接触区（31）位于欧姆接触之下，进一步将二极管结耦合到欧姆接触。 优选地，二极管结是铂 - 硅化物结。 改进的肖特基二极管结构可以形成为BICMOS集成电路制造工艺的一部分，其中埋入二极管层可以与双极晶体管结构的掩埋集电极层同时形成，二极管NWell可以同时形成 作为CMOS晶体管结构的NWell，并且二极管欧姆接触区域可以在集电极阱区域的同时形成。 在BICMOS制造工艺中，埋地集电极层定义掩模也是埋地二极管层定义掩模，复古NWell定义掩模也是二极管NWell定义掩模，集电极阱定义掩模也是二极管欧姆接触区域定义掩模，而 BICMOS触点定义掩码也是二极管结和欧姆接触定义掩码。
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