公开(公告)号：EP3170207A4

公开(公告)日：2018-03-28

申请号：EP14897867

申请日：2014-07-14

申请人： INTEL CORP

发明人： HAFEZ WALID M ,  JAN CHIA HONG

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

摘要： A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.

公开(公告)号：EP1184910A3

公开(公告)日：2004-10-13

申请号：EP01307059.4

申请日：2001-08-20

申请人： Agere Systems Guardian Corporation

发明人： Krutsick, Thomas J.

IPC分类号： H01L29/8605 ,  H01L29/06 ,  H01L27/08 ,  H01L21/02 ,  H01L23/522

CPC分类号： H01L29/66166 ,  H01L29/8605

摘要： An integrated circuit includes a field plated resistor having enhanced area thereover for routing metal conductors, formed in the same layer of metal as forms contacts to the resistor, is fabricated by a sequence of processing steps. A resistor having a resistor body and a contact region at each end thereof is formed in an active region of a semiconductor substrate. A first layer of insulative material is formed over the resistor and a window is created through the first layer of insulative material to the resistor body to form a first contact region. A layer of polysilicon is formed over the first insulative layer to define a field plate, the polysilicon field plate being contiguous with the first contact region of the resistor and extending over the resistor body to substantially to the other contact region, as layout, design, and fabrication rules permit. A second insulative layer is formed over the polysilicon layer. Windows are created in the second insulative layer to provide access to the polysilicon field plate and the second contact region. A metal layer is applied and unwanted metal is etched away to provide conductors over the polysilicon field plate of a field plated resistor having enhanced area thereover for routing metal conductors formed in the same layer of metal as forms contacts to the resistor.

公开(公告)号：EP1184909A2

公开(公告)日：2002-03-06

申请号：EP01307010.7

申请日：2001-08-17

申请人： Agere Systems Guardian Corporation

发明人： Krutsick, Thomas J

IPC分类号： H01L29/8605 ,  H01L29/06

CPC分类号： H01L29/66166 ,  H01L29/8605

摘要： An integrated circuit includes a field plated resistor having enhanced area thereover for routing metal conductors, formed in the same layer of metal as forms contacts to the resistor, is fabricated by a sequence of processing steps. A resistor having a resistor body and a contact region at each end thereof is formed in an active region of a semiconductor substrate. A first layer of insulative material is formed over the resistor and a window is created through the first layer of insulative material to the resistor body to form a first contact region. A layer of polysilicon is formed over the first insulative layer to define a field plate, the polysilicon field plate being contiguous with the first contact region of the resistor and extending over the resistor body to substantially to the other contact region, as layout, design, and fabrication rules permit. A second insulative layer is formed over the polysilicon layer. Windows are created in the second insulative layer to provide access to the polysilicon field plate and the second contact region. A metal layer is applied and unwanted metal is etched away to provide conductors over the polysilicon field plate of a field plated resistor having enhanced area thereover for routing metal conductors formed in the same layer of metal as forms contacts to the resistor.

摘要翻译： 集成电路包括具有增强区域的场地电镀电阻器，用于布置金属导体，其形成在与电阻器形成接触的金属相同的金属层中，通过一系列处理步骤制造。 在半导体基板的有源区域中形成有在其两端具有电阻体和接触区域的电阻体。 第一层绝缘材料形成在电阻器上方，并且通过第一绝缘材料层产生窗口到电阻体以形成第一接触区域。 在第一绝缘层上形成多晶硅层以限定场板，多晶硅场板与电阻器的第一接触区域相邻并且在电阻器主体上延伸到基本上到另一个接触区域，作为布局，设计， 制造规则允许。 在多晶硅层上形成第二绝缘层。 在第二绝缘层中创建窗口以提供对多晶硅场板和第二接触区域的访问。 施加金属层，并且不需要的金属被蚀刻掉，以在其上具有增强区域的场电镀电阻器的多晶硅场板上提供导体，用于布置形成在与形成接触电阻器的金属相同的金属层中的金属导体。

公开(公告)号：EP0465151A2

公开(公告)日：1992-01-08

申请号：EP91305868.1

申请日：1991-06-28

申请人： CANON KABUSHIKI KAISHA

发明人： Nakamura, Yoshio ,  Kikuchi, Shin ,  Nishimura, Shigeru

IPC分类号： H01L29/91 ,  H01L29/73 ,  H01L29/784 ,  H01L29/56 ,  H01L29/48 ,  H01L21/285 ,  H01L29/40

CPC分类号： H01L29/66166 ,  H01L21/28537 ,  H01L29/47 ,  H01L29/7308 ,  H01L29/7839 ,  H01L29/872

摘要： A semiconductor device having a Shottky junction comprises: a first semiconductor area composed of an n-type semiconductor; a second semiconductor area composed of an n-type semiconductor of a higher resistance than in said first semiconductor area; an insulation film provided adjacent to said second semiconductor area and having an aperture therein; an electrode area provided in said aperture; and a third semiconductor area composed of a p-type semiconductor provided at the junction between said insulation film and said electrode area.
The electrode area is composed of a monocrystalline metal and constitutes a Shottky junction with said second semiconductor area.

摘要翻译： 具有肖特基结的半导体器件包括：由n型半导体构成的第一半导体区域; 由比所述第一半导体区域高的电阻的n型半导体构成的第二半导体区域; 设置在所述第二半导体区域附近并在其中具有孔的绝缘膜; 设置在所述孔中的电极区域; 以及由设置在所述绝缘膜和所述电极区域之间的接合处的p型半导体构成的第三半导体区域。 电极区域由单晶金属构成，与所述第二半导体区域构成肖特基结。

公开(公告)号：EP0443297A1

公开(公告)日：1991-08-28

申请号：EP90830063.5

申请日：1990-02-20

申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

发明人： Santangelo, Antonello ,  Magro, Carmelo ,  Ferla, Giuseppe ,  Lanza, Paolo

IPC分类号： H01L21/285 ,  H01L21/60

CPC分类号： H01L29/66166 ,  H01L21/28518 ,  H01L21/76879

摘要： The process consists of enrichment of the surface of the semiconductor on which the contact is to be formed, by ion implantation of dopant, followed by deposition of a metal film on the implanted surface and then by thermal annealing at a temperature considerably lower than 500 °C and for a period considerably shorter than 60 minutes.

摘要翻译： 该方法包括通过离子注入掺杂剂富集待形成接触的半导体的表面，然后在注入的表面上沉积金属膜，然后在显着低于500℃的温度下进行热退火 并且持续时间大大短于60分钟。

公开(公告)号：EP0443297B1

公开(公告)日：1999-09-01

申请号：EP90830063.5

申请日：1990-02-20

申请人： STMicroelectronics S.r.l.

发明人： Santangelo, Antonello ,  Magro, Carmelo ,  Ferla, Giuseppe ,  Lanza, Paolo

IPC分类号： H01L21/285 ,  H01L21/60

CPC分类号： H01L29/66166 ,  H01L21/28518 ,  H01L21/76879

公开(公告)号：EP0455376B1

公开(公告)日：1997-10-15

申请号：EP91303388.2

申请日：1991-04-16

申请人： DIGITAL EQUIPMENT CORPORATION

发明人： Zetterlund, Bjorn K.A.

IPC分类号： H01L21/82 ,  H01L29/86 ,  H01C17/06

CPC分类号： H01L29/66166 ,  H01L21/8238 ,  H01L27/0629

公开(公告)号：EP0545363A1

公开(公告)日：1993-06-09

申请号：EP92120493.9

申请日：1992-12-01

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Robinson, Murray J. ,  Joyce, Christopher C.

IPC分类号： H01L21/329 ,  H01L21/82 ,  H01L27/06

CPC分类号： H01L29/66166 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0629 ,  H01L27/0928

摘要： A high definition, high resistance resistor structure is formed in a resistor PWell by shallowly implanting a well-defined resistive region of the resistor PWell with relatively fast-diffusing N type atoms in an N⁻ concentration, and shallowly implanting a well-defined resistor contacts regions with relatively slow-diffusing N type atoms in an N⁺ concentration. The high definition, high resistance resistor structure (2) fabrication steps are integrated into MOS transistor structure fabrication steps without adding any new steps to the process. The resistor PWell is formed at the same time as the MOS transistor structure PWell, the resistive region is implanted at the same time as the low density drain (LDD) regions for the MOS device, and the resistor contacts regions are implanted at the same time as the source and drain regions of the MOS transistor structure. MOS transistor masks are modified to include a resistor PWell definition opening, a resistive region definition opening, resistor contacts regions definition openings, and resistor contacts definition openings.

摘要翻译： 通过以N +浓度相对快速扩散的N型原子浅埋入电阻器PWell的良好限定的电阻区域，在电阻器PWell中形成高清晰度，高电阻电阻器结构，并且浅埋入良好的 具有N +浓度相对缓慢扩散的N型原子的电阻器接触区域。 高清晰度，高电阻电阻结构（2）制造步骤集成到MOS晶体管结构制造步骤中，而不需要为工艺增加任何新的步骤。 电阻器PWell与MOS晶体管结构PWell同时形成，电阻区域与MOS器件的低密度漏极（LDD）区域同时注入，并且电阻器接触区域同时被注入 作为MOS晶体管结构的源极和漏极区域。 MOS晶体管掩模被修改为包括电阻器PWell定义开口，电阻区域定义开口，电阻器触点区域定义开口和电阻器触点定义开口。

公开(公告)号：EP0437949A1

公开(公告)日：1991-07-24

申请号：EP90313694.3

申请日：1990-12-14

申请人： HONEYWELL INC.

发明人： Johnson, Ralph H.

IPC分类号： H01L21/74 ,  H01L21/22

CPC分类号： H01L29/66166 ,  H01L21/743

摘要： A structure and a device which allow low resistance connection to internal circuit devices comprising a double diffused leadout is described. The first leadout diffusion (17,18) is lightly doped with dopant from either chemical group III or V to constitute N- or P- type material respectively. The lightly doped region has a high resistivity. The second diffusion (13,14) is diffused, using a dopant from the same chemical group as the first dopant, into the first diffusion. The second diffusion is diffused with enough dopant to constitute N + or P + material and has a low resistivity. The double diffused leadout creates a low resistance connection to the internal circuitry of an IC device while maintaining breakdown with the protective overlayer (31).

摘要翻译： 描述了允许与包括双扩散引出件的内部电路装置的低电阻连接的结构和装置。 第一引出扩散（17,18）分别用化学III或V族的掺杂剂轻掺杂以构成N-或P-型材料。 轻掺杂区域具有高电阻率。 使用与第一掺杂剂相同的化学基团的掺杂剂将第二扩散（13,14）扩散到第一扩散中。 第二扩散部分用足够的掺杂剂扩散以构成N +或P +材料，并具有低电阻率。 双扩散引出产生与IC器件的内部电路的低电阻连接，同时保护与保护覆层（31）的击穿。

公开(公告)号：EP0398333A3

公开(公告)日：1991-03-27

申请号：EP90109346.8

申请日：1990-05-17

申请人： FUJITSU LIMITED

发明人： Nakamura, Shunji, Moakurasuto-Tamagawagakuen 1-112

IPC分类号： H01L21/3205 ,  H01L21/336

CPC分类号： H01L28/20 ,  H01L29/66166 ,  H01L29/66757

摘要： A semiconductor resistance element of one electrical conduction type comprises: a semiconductor region including a first impurity of opposite electrical conduction type and second impurity of one electrical conduction type, wherein said second impurity is more heavily introduced so that a predetermined resistance is obtained; and electrode regions provided on both ends of said semiconductor region.