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    Voltage controlled oscillation ciruit
    2.
    发明公开
    Voltage controlled oscillation ciruit 审中-公开
    Spannungsgesteuerter振荡器

    公开(公告)号：EP0930707A1

    公开(公告)日：1999-07-21

    申请号：EP99100644.6

    申请日：1999-01-14

    申请人： NIPPON PRECISION CIRCUITS INC.

    发明人： Ueno, Naoki c/o Nippon Precision Circuits Inc.

    IPC分类号： H03K3/282 ,  H03K3/0231 ,  H03K3/012

    CPC分类号： H03K3/2821 ,  H03K3/0231

    摘要： Increase of frequency and reduction of power consumption are advanced for a voltage controlled oscillation circuit. A capacitor C1 is connected between emitters of first and second transistors Tr1, Tr2 to receive an electric current from a constant current source Cs1, Cs2. Also, emitters of third and fourth transistors Tr3, Tr4 having respective collectors connected through third and fourth resistors R3, R4 to a power supply terminal VCC. The respective collectors and bases of the third and fourth transistors Tr3, Tr4 are connected to bases and collectors of the first and second transistors Tr1, Tr2. Due to this, oscillation outputs are caused at respective ends of the capacitor C1, which has a voltage amplitude equal to a voltage drop due to the third and fourth resistors R3, R4 and values of currents flowing through them. The voltage drop can be decreased to such an extent that the first and second transistors Tr1, Tr2 can be turned on. Also, the voltage drop due to the first and second resistors R1, R2 and the current flowing through them can be decreased to such an extent that the third and fourth transistors Tr3, Tr4 can be turned on. This decreases the resistance value of each resistor and the value of the current flowing therethrough to thereby increase the operating speed, advancing power consumption.

    摘要翻译： 对于压控振荡电路，提高频率和降低功耗是先进的。 电容器C1连接在第一和第二晶体管Tr1，Tr2的发射极之间，以接收来自恒流源Cs1，Cs2的电流。 此外，具有通过第三和第四电阻器R3，R4连接到电源端子VCC的各个集电极的第三和第四晶体管Tr3，Tr4的发射极。 第三和第四晶体管Tr3，Tr4的各个集电极和基极连接到第一和第二晶体管Tr1，Tr2的基极和集电极。 由此，在电容器C1的各端产生振荡输出，其电压幅度等于由于第三和第四电阻器R3，R4的电压降和流过它们的电流值。 电压降可以降低到可以使第一和第二晶体管Tr1，Tr2导通的程度。 此外，由于第一和第二电阻器R1，R2以及流过它们的电流引起的电压降可以减小到可以使第三和第四晶体管Tr3，Tr4导通的程度。 这降低了每个电阻器的电阻值和流过其中的电流值，从而提高了运行速度，提高了功耗。

    Frequency divider
    3.
    发明公开
    Frequency divider 有权
    分频器

    公开(公告)号：EP0918395A2

    公开(公告)日：1999-05-26

    申请号：EP98121452.1

    申请日：1998-11-11

    申请人： NIPPON PRECISION CIRCUITS INC.

    发明人： Ueno, Naoki c/o Nippon Precision Circuits Inc.

    IPC分类号： H03K23/66

    CPC分类号： H03K23/505

    摘要： There is disclosed a frequency divider that operates at an improved operating speed and provides frequency division given with a frequency division ratio of N, where N is an odd number. The frequency divider comprises first, second, and third stages of D-type flip-flops. The first stage selects either the output from the second stage or the output from the third stage according to the logic level of the output from the third stage. Delay is eliminated from between the first and third stages and from between the first and second stages. Consequently, the operating frequency can be enhanced.