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公开(公告)号：EP0918395B1
公开(公告)日：2003-01-22
申请号：EP98121452.1
申请日：1998-11-11
IPC分类号： H03K23/66
CPC分类号： H03K23/505
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公开(公告)号：EP0920132B1
公开(公告)日：2002-03-27
申请号：EP98120752.5
申请日：1998-11-02
发明人： Tsukagoshi, Kunihiko c/o Nippon Precision Circuits , Miyabe, Satoru c/o Nippon Precision Circuits Inc. , Oyama, Kazuhisa c/o Nippon Precision Circuits Inc.
IPC分类号： H03K19/003 , H03K19/094 , H03K19/00
CPC分类号： H03K19/0013 , H03K19/00323 , H03K19/09429
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公开(公告)号：EP0920132A1
公开(公告)日：1999-06-02
申请号：EP98120752.5
申请日：1998-11-02
发明人： Tsukagoshi, Kunihiko c/o Nippon Precision Circuits , Miyabe, Satoru c/o Nippon Precision Circuits Inc. , Oyama, Kazuhisa c/o Nippon Precision Circuits Inc.
IPC分类号： H03K19/003 , H03K19/094 , H03K19/00
CPC分类号： H03K19/0013 , H03K19/00323 , H03K19/09429
摘要： The drains of P- and N-channel MOS transistors 1 and 2 are connected to each other. An output terminal is formed at the node of the drains. Each of first and second amplifier stages 4 and 5 is configured by cascading an n number of CMOS inverters. The amplifier stages drive first and second last-stage CMOS inverters 6 and 7 to drive the P- and N-channel MOS transistors 1 and 2, respectively. A dummy CMOS inverter 8 is disposed so that the input is connected to the node of the second amplifier stage 5 and the second last-stage CMOS inverter 7. The load of the second amplifier stage 5 is equal to that of the first amplifier stage 4. The drivabilities of the CMOS inverters of the same stage in the first and second amplifier stages 4 and 5 are made equal to each other. According to this configuration, the number of CMOS inverters which must be checked in a process of adjusting the duty can be reduced.
摘要翻译： P沟道和N沟道MOS晶体管1和2的漏极相互连接。 输出端子形成在排水管的节点处。 第一和第二放大器级4和5中的每一个通过级联n个CMOS反相器来配置。 放大器级驱动第一和第二后级CMOS反相器6和7，分别驱动P沟道MOS晶体管和N沟道MOS晶体管1和2。 虚设CMOS反相器8被布置成使得输入端连接到第二放大器级5和第二最后级CMOS反相器7的节点。第二放大器级5的负载等于第一放大器级4的负载 使第一和第二放大器级4和5中相同级的CMOS反相器的驱动能力彼此相等。 根据该结构，可以减少在调整占空比的过程中必须检查的CMOS反相器的数量。
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公开(公告)号：EP1133062A3
公开(公告)日：2004-02-25
申请号：EP01105605.8
申请日：2001-03-06
发明人： Takeda, Minoru, Nippon Precision Circuits Inc. , Fujiwara, Kazuyuki, Nippon Precision Circuits Inc.
摘要： In a delta sigma type D/A converter, in order to be capable of carrying out muting operation in steps at steps lower than 1 quantized step by digital processing, a multiplexor 2 for selectively outputting a mute code 15 for making an analog signal null and a thermometer code 14 to a local DAC4 is provided between a thermometer code converter 1 and the local DAC4, a time period of 1/M of a sampling period is made to constitute 1 cycle, at m1 (0≤m1≤M) cycle, the thermometer code 14 is made an output of the multiplexor 2 and at other m2 (m2=M-m1) cycle, the mute code 15 is made an output thereof and muting is carried out by reducing the ml cycle or muting is relieved by increasing thereof in steps at respective sampling period.
摘要翻译： 在ΔΣ型D / A转换器中，为了能够通过数字处理以低于1量化步长的步骤执行静噪操作，多路复用器2用于选择性地输出用于使模拟信号为空的静音代码15和 在温度计代码转换器1和本地DAC4之间设置温度计代码14到本地DAC4，在m1（0≤m1≤M）周期，使采样周期的1 / M的时间周期构成1个周期， 使温度计代码14成为多路复用器2的输出，在其他m2（m2 = M-m1）周期，使静音代码15作为其输出，并通过减少ml周期来实现静音，或通过增加静音 在相应的采样周期的步骤。
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5.发明公开Method of controlling laser diode in optical disk player and circuit therefor 审中-公开在光盘播放器及其电路控制激光二极管的方法
公开(公告)号：EP1162611A2
公开(公告)日：2001-12-12
申请号：EP01113763.5
申请日：2001-06-05
IPC分类号： G11B7/125
CPC分类号： G11B11/10595 , G11B7/005 , G11B7/08511 , G11B7/1263 , G11B11/10515
摘要： Electric power consumed by a laser diode when an optical disk or magneto-optical disk is played back is reduced. A laser diode control circuit (6) causes the laser diode to emit continuously rather than intermittently, even if a PCK signal is supplied to the laser diode control circuit (6), when an optical display player or magneto-optical disk drive does not yet stabilize and is being pulled into a phase-locked state. When the focus is locked, the player is in a phase-locked state, and the operation is stable, a mode-switching circuit (9) included in the laser diode control circuit (6) switches the mode of operation from continuous operation to intermittent operation according to an FLOCK signal. The frequency of the PCK is multiplied by a frequency multiplier circuit (7), and the pulse width is adjusted by a pulse width-adjusting circuit (8). A laser diode driver circuit (10) produces intermittent current of this adjusted pulse width. The laser diode is started to emit intermittently.
摘要翻译： 由激光二极管消耗当光盘或磁光盘是唇同步的减小电力。 的激光二极管控制电路（6）使激光二极管以发射连续而非间歇地，即使一个PCK信号被提供给激光二极管控制电路（6）当一种光学显示播放器或磁光盘驱动器尚不 稳定并被拉入相位锁定状态。 当焦点被锁定时，播放器处于锁相状态，手术是稳定的，一模式转换电路（9）包括在激光二极管控制电路（6）的间歇切换操作从continuousOperation到模式 操作gemäß在FLOCK信号。 的PCK的频率由频率乘法器电路（7）相乘，脉冲宽度是由脉冲宽度调节电路（8）进行调节。 激光二极管驱动器电路（10）产生该调整的脉冲宽度的断续电流。 激光二极管开始间歇性地发射。
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公开(公告)号：EP1133062A2
公开(公告)日：2001-09-12
申请号：EP01105605.8
申请日：2001-03-06
发明人： Takeda, Minoru, Nippon Precision Circuits Inc. , Fujiwara, Kazuyuki, Nippon Precision Circuits Inc.
IPC分类号： H03M3/04
摘要： In a delta sigma type D/A converter, in order to be capable of carrying out muting operation in steps at steps lower than 1 quantized step by digital processing, a multiplexor 2 for selectively outputting a mute code 15 for making an analog signal null and a thermometer code 14 to a local DAC4 is provided between a thermometer code converter 1 and the local DAC4, a time period of 1/M of a sampling period is made to constitute 1 cycle, at m1 (0≤m1≤M) cycle, the thermometer code 14 is made an output of the multiplexor 2 and at other m2 (m2=M-m1) cycle, the mute code 15 is made an output thereof and muting is carried out by reducing the ml cycle or muting is relieved by increasing thereof in steps at respective sampling period.
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公开(公告)号：EP0930707A1
公开(公告)日：1999-07-21
申请号：EP99100644.6
申请日：1999-01-14
IPC分类号： H03K3/282 , H03K3/0231 , H03K3/012
CPC分类号： H03K3/2821 , H03K3/0231
摘要： Increase of frequency and reduction of power consumption are advanced for a voltage controlled oscillation circuit. A capacitor C1 is connected between emitters of first and second transistors Tr1, Tr2 to receive an electric current from a constant current source Cs1, Cs2. Also, emitters of third and fourth transistors Tr3, Tr4 having respective collectors connected through third and fourth resistors R3, R4 to a power supply terminal VCC. The respective collectors and bases of the third and fourth transistors Tr3, Tr4 are connected to bases and collectors of the first and second transistors Tr1, Tr2. Due to this, oscillation outputs are caused at respective ends of the capacitor C1, which has a voltage amplitude equal to a voltage drop due to the third and fourth resistors R3, R4 and values of currents flowing through them. The voltage drop can be decreased to such an extent that the first and second transistors Tr1, Tr2 can be turned on. Also, the voltage drop due to the first and second resistors R1, R2 and the current flowing through them can be decreased to such an extent that the third and fourth transistors Tr3, Tr4 can be turned on. This decreases the resistance value of each resistor and the value of the current flowing therethrough to thereby increase the operating speed, advancing power consumption.
摘要翻译： 对于压控振荡电路，提高频率和降低功耗是先进的。 电容器C1连接在第一和第二晶体管Tr1，Tr2的发射极之间，以接收来自恒流源Cs1，Cs2的电流。 此外，具有通过第三和第四电阻器R3，R4连接到电源端子VCC的各个集电极的第三和第四晶体管Tr3，Tr4的发射极。 第三和第四晶体管Tr3，Tr4的各个集电极和基极连接到第一和第二晶体管Tr1，Tr2的基极和集电极。 由此，在电容器C1的各端产生振荡输出，其电压幅度等于由于第三和第四电阻器R3，R4的电压降和流过它们的电流值。 电压降可以降低到可以使第一和第二晶体管Tr1，Tr2导通的程度。 此外，由于第一和第二电阻器R1，R2以及流过它们的电流引起的电压降可以减小到可以使第三和第四晶体管Tr3，Tr4导通的程度。 这降低了每个电阻器的电阻值和流过其中的电流值，从而提高了运行速度，提高了功耗。
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公开(公告)号：EP0918395A2
公开(公告)日：1999-05-26
申请号：EP98121452.1
申请日：1998-11-11
IPC分类号： H03K23/66
CPC分类号： H03K23/505
摘要： There is disclosed a frequency divider that operates at an improved operating speed and provides frequency division given with a frequency division ratio of N, where N is an odd number. The frequency divider comprises first, second, and third stages of D-type flip-flops. The first stage selects either the output from the second stage or the output from the third stage according to the logic level of the output from the third stage. Delay is eliminated from between the first and third stages and from between the first and second stages. Consequently, the operating frequency can be enhanced.
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公开(公告)号：EP0669057A1
公开(公告)日：1995-08-30
申请号：EP94901341.0
申请日：1993-11-08
IPC分类号： H03K19
CPC分类号： H03K19/17712
摘要： A programmable logic device (PLD) and configurable logic network in which one or more logic combination networks (LCN) each receives logic inputs from two or more PLDs (PLD1, PLD2) and generates logic outputs (O, P) which can then be used to provide inputs to programmable logic networks (POR, UCL,...) for implementing logic functions of various types and functionality. Each programmable logic device includes an AND logic array (FAND...) having inputs for receiving signals (Ax, Bx) and generating product term output signals and an OR logic array (OG...) having inputs for receiving signals and generating sum term output signals (OF...). One or both of the AND logic and OR logic arrays is programmable and the logic arrays are interconnected to apply output signals from one of them as input signals to the other one, the output from which provides PLD output signals. The logic combination networks may be fixed logic networks (LCN100) or programmable logic function generators (UBLFG20, UBFF2P) that produce outputs controlled by a set of programmable inputs (CNx, DNx) to the generator as a function of the logic inputs (O, P) received from the programmable logic devices.
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公开(公告)号：EP0669055A1
公开(公告)日：1995-08-30
申请号：EP94901340.0
申请日：1993-11-08
CPC分类号： H03K19/17704
摘要： A logic system comprising one or more logic networks (LNA0..LNA3) that can perform a variety of logic functions, either by configuration of a multi-function network or by a switched network comprising several sub-networks each of which performs one or more dedicated logic functions. Each logic network is functionally separate from but operatively associated with one or more programmable circuits (PROG) from which that logic network receives logic control signals (LSFA0..LSFA3) to select a particular logic function or functions to be performed by the logic network(s). The programmable circuit also supplies separate logic signals (LSCA0..LSCA3) to control the operation of the logic network(s) in implementing the selected logic function. In this manner the programmable circuit (PROG) can essentially be dedicated to selecting the function and controlling the operation of the selected function of the logic network(s) and is relieved of significant functional overhead associated with data manipulation typically performed by conventional operation of logic network(s). This can permit a smaller size programmable logic, gate or memory array to be used to control a logic operation of a given complexity, or a given size of array to control more complex operations. Both the programmable circuit(s) and the logic network(s) can be integrated in a single semiconductor chip.
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