公开(公告)号：EP0604651A4

公开(公告)日：1995-04-19

申请号：EP92915839

申请日：1992-07-16

申请人： NIPPON SIGNAL CO LTD ,  ESASHI MASAYOSHI

发明人： ESASHI MASAYOSHI-YAGIYAMAMIN ,  ASADA NORIHIRO YONO OFFICE NIP ,  KATO MASAKAZU YONO OFFICE NIPP ,  FUTUHARA KOICHI YONO OFFICE NI

IPC分类号： H03K19/007

CPC分类号： H03K19/007

摘要： A fail-safe logical operation circuit which includes a transformer (T) for converting binary input signals to magnetic flux to sum them up, and a level detector (1) for detecting this sum and generating binary outputs having logical values of "1" and "0". In this way, the fail-safe circuit can simplify the circuit construction and can reduce the level of the logical output.