公开(公告)号：EP3053271A4

公开(公告)日：2017-06-28

申请号：EP14851322

申请日：2014-09-29

申请人： TEXAS INSTRUMENTS INC

发明人： RAJAGOPAL DEVRAJ MATHARAMPALLIL ,  PARTHASARATHY RAJAGOPALAN

IPC分类号： H03K17/56 ,  H03K19/007 ,  H03K19/0185

CPC分类号： H03K19/007 ,  H03K19/018521

摘要： An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

摘要翻译： 由输入/输出（IO）供电电压供电的输入/输出（IO）电路。 IO电路包括检测内核电源电压并产生电源检测信号的电源检测器单元。 驱动器电路连接到PAD，驱动器电路接收电源检测信号。 故障保护电路接收PAD电压。 基于IO电源电压和PAD电压，故障保护电路和电源检测器单元控制来自PAD的泄漏电流。

公开(公告)号：EP3014365A1

公开(公告)日：2016-05-04

申请号：EP14732171.5

申请日：2014-06-20

申请人： Pilz GmbH & Co. KG

发明人： VEIL, Richard ,  SEIZINGER, Dietmar ,  KLUGE, Marco

IPC分类号： G05B9/03 ,  G05B19/05

CPC分类号： H01H71/10 ,  G05B9/03 ,  G05B19/058 ,  G05B2219/14048 ,  G05B2219/14054 ,  H03K19/007

摘要： The invention relates to a safety switching device (10) for deactivating a technical system (12) in a failsafe manner, comprising a first and at least one second input (30, 30'). The first input (30) receives a first input signal (38) by means of a first input circuit (32), and the second input (30') receives a second input signal (38') by means of a second input circuit. The first and second input circuit are divided into a first (I) and a second circuit (II) which are galvanically separated from each other. A first signal input circuit (40), a first threshold element (44), and a first coupling element (42) of the first input circuit (32) as well as a second signal input circuit (40'), a second threshold element (44'), and a second coupling element (42') of the second input circuit are arranged in the first circuit (I). The first circuit (I) further has a first testing device (46) with a third coupling element (48), the first testing device (46) being designed to interrupt a current path from the first and second threshold element (44, 44') to a ground terminal (64). A second testing device (52) and a first discharge circuit (54) of the first input (30) and a third testing device (52') and a second discharge circuit (54') of the second input are arranged in the second circuit (II), said first, second, and third coupling element (42, 42', 48) connecting the first and second circuit (I, II) to each other. (Fig. 1)

公开(公告)号：EP2033316A4

公开(公告)日：2010-08-11

申请号：EP07796326

申请日：2007-06-20

申请人： ELEMENT CXI LLC

发明人： KELEM STEVEN HENNICK ,  CUMMINS JAIME C ,  WATSON JOHN L ,  PLUNKETT ROBERT ,  WASSON STEPHEN L ,  BOX BRIAN A ,  WEIN ENNO ,  FURCINITI CHARLES A

IPC分类号： G01R31/28 ,  G06F9/38 ,  G06F15/78 ,  H03K19/177

CPC分类号： G06F9/5083 ,  G06F9/4881 ,  G06F15/17362 ,  G06F15/7867 ,  G06F17/5077 ,  H03K19/003 ,  H03K19/007 ,  H03K19/173 ,  H03K19/17748 ,  H03K19/17764 ,  Y02D10/12 ,  Y02D10/13

摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

公开(公告)号：EP2033316A2

公开(公告)日：2009-03-11

申请号：EP07796326.2

申请日：2007-06-20

申请人： Element CXI, LLC

发明人： KELEM, Steven, Hennick ,  CUMMINS, Jaime, C. ,  WATSON, John, L. ,  PLUNKETT, Robert ,  WASSON, Stephen, L. ,  BOX, Brian, A. ,  WEIN, Enno ,  FURCINITI, Charles, A.

IPC分类号： H03K19/177

CPC分类号： G06F9/5083 ,  G06F9/4881 ,  G06F15/17362 ,  G06F15/7867 ,  G06F17/5077 ,  H03K19/003 ,  H03K19/007 ,  H03K19/173 ,  H03K19/17748 ,  H03K19/17764 ,  Y02D10/12 ,  Y02D10/13

摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

公开(公告)号：EP2020085A2

公开(公告)日：2009-02-04

申请号：EP07761447.7

申请日：2007-04-27

申请人： Achronix Semiconductor Corp.

发明人： MANOHAR, Rajit ,  KELLY, Clinton W.

IPC分类号： H03K19/003

CPC分类号： G11C11/4125 ,  H03K19/00338 ,  H03K19/007 ,  H03K19/20

摘要： New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single - event effects SEE-tolerant configurations (210, 210', 301,404, 510, 520, 800) are shown and described for combinational logic circuits and state-holding logic circuits The invention further provides SEE-tolerant configurations for SRAM memory circuits (700, 800)

公开(公告)号：EP1233516B1

公开(公告)日：2007-01-24

申请号：EP02002870.0

申请日：2002-02-08

申请人： Siemens Schweiz AG

发明人： Ellenberger, Peter

IPC分类号： H03K19/007

CPC分类号： H03K19/007

公开(公告)号：EP0604651A4

公开(公告)日：1995-04-19

申请号：EP92915839

申请日：1992-07-16

申请人： NIPPON SIGNAL CO LTD ,  ESASHI MASAYOSHI

发明人： ESASHI MASAYOSHI-YAGIYAMAMIN ,  ASADA NORIHIRO YONO OFFICE NIP ,  KATO MASAKAZU YONO OFFICE NIPP ,  FUTUHARA KOICHI YONO OFFICE NI

IPC分类号： H03K19/007

CPC分类号： H03K19/007

摘要： A fail-safe logical operation circuit which includes a transformer (T) for converting binary input signals to magnetic flux to sum them up, and a level detector (1) for detecting this sum and generating binary outputs having logical values of "1" and "0". In this way, the fail-safe circuit can simplify the circuit construction and can reduce the level of the logical output.

公开(公告)号：EP0498248A1

公开(公告)日：1992-08-12

申请号：EP92101252.2

申请日：1992-01-27

申请人： HITACHI, LTD.

发明人： Nomi, Makoto

IPC分类号： H03K19/007

CPC分类号： H03K19/007

摘要： A fail-safe logic circuit required to assure security in a system requiring high safety such as an automatic railway control system is constructed by a conventional digital IC. A plurality of flip-flops (1a, 1b) are connected in series, an output of a final stage flip-flop (1b) is inverted and connected to an input of a first stage flip-flop (1a), and pulse signals (Xa, Xb) representing logical inputs are applied to clock terminals (T) of the respective flip-flops so that an output representing a combination of the input states is produced at the output of the final stage flip-flop (1b). The fail-safe logic circuit is constructed by the flip-flops which are in the form of simple digital IC and input pulse signals. Thus, the fail-safe function is attained with the simple circuit and the safety feature of the system is enhanced.

摘要翻译： 通过传统的数字IC构造一个故障安全逻辑电路，以确保需要高安全性的系统（如自动化铁路控制系统）的安全性。 多个触发器（1a，1b）串联连接，最终级触发器（1b）的输出反相并连接到第一级触发器（1a）的输入端，并将脉冲信号（ Xa，Xb）被施加到各个触发器的时钟端子（T），使得在最终级触发器（1b）的输出处产生表示输入状态的组合的输出。 故障保护逻辑电路由简单数字IC和输入脉冲信号形式的触发器构成。 因此，通过简单的电路实现了故障安全功能，提高了系统的安全性。

公开(公告)号：EP0195705A1

公开(公告)日：1986-09-24

申请号：EP86400441.1

申请日：1986-03-04

申请人： JEUMONT-SCHNEIDER Société anonyme dite:

发明人： Guillaumin, Jacques

IPC分类号： H03K19/007

CPC分类号： H03K19/007

摘要： 57 Selon l'invention, le circuit logique engendrant un courant continu d'intensité maximale déterminée sur sa borne de sortie (E) lorsqu'un signal alternatif d'amplitude quelconque est appliqué à sa borne d'entrée (El) comprend un convertisseur (12,13), non référencé en tension continue par rapport à la masse, un condensateur (11) connecté entre la borne de sortie positive et la borne de sortie négative dudit convertisseur, un générateur de courant constant (23,24) connecté entre ladite borne de sortie positive et la masse, ladite borne de sortie négative constituant la borne de sortie dudit circuit logique.

公开(公告)号：EP0049679A1

公开(公告)日：1982-04-14

申请号：EP81730094.0

申请日：1981-09-18

申请人： Licentia Patent-Verwaltungs-GmbH

发明人： Lotz, Alfred, Ing. grad.

IPC分类号： H03K19/007

CPC分类号： H03K19/007

摘要： Die Anmeldung bezieht sich auf eine Schaltungsanordnung zur logischen Verknüpfung wechselspannungsförmiger Eingangssignale zu einem wechselspannungsförmigen Ausgangssignal durch Gleichrichtung der Eingangssignale zu einem Gleichstromsignal, das eine Schwingungsschaltung mit Verstärker steuert. Die Erfindung besteht darin, daß an den Eingängen zur galvanischen Trennung Kondensatoren (5, 6) mit 4 diagonal genenüberliegenden Anschlüssen vorgesehen sind, wobei an einem Belag die Eingänge (E1, E2) und an einem zweiten Belag Gleichrichterschaltungen aus entgegengesetzt gepolten Dioden (7, 8, 9, 10) angeschlossen sind, die mit Glättungsschaltungen aus Kondensatoren (11, 12) mit 4 diagonal gegenüberliegenden Anschlüssen und Zener-Dioden (15, 16) zur Stabilisierung verbunden sind, die an eine Oszillatorschaltung (17) vor dem Ausgang angeschlossen sind. Jeweils ein Eingang ist an einer anderen logischen Verknüpfungsschaltung seriell geschleift. Die Dotierung wird so gewählt, daß die zur Erzeugung der Eingangswechselspannungssignale verwendete Batteriespannung jeweils die entgegengesetzte Polung zu den von der Oszillatorschaltung benötigten und in Abhängigkeit von den Wechselspannungssignalen durch die Eingangskondensatoren und Gleichrichterschaltungen erzeugten Betriebsspannungen aufweist.

摘要翻译： 本申请涉及用于逻辑组合交流电压形输入信号以通过整流输入信号形成交流电压形状的输出信号以形成用放大器控制振荡电路的直流信号的电路装置。 本发明的目的在于，在输入端设有具有4个对角线相对端子的电容器（5,6）用于实现直流隔离，输入端（E1，E2）连接到一个极板和相对极化二极管（7）的整流电路 ，8,9,10）连接到另一个板，这些二极管连接到具有4个对角线相对端子的电容器（11,12）的平滑电路和用于稳定的齐纳二极管（15,16），其连接到振荡器电路 （17）在输出之前。 每种情况下的一个输入串行循环到另一个逻辑组合电路。 以这样的方式选择掺杂，使得用于在每种情况下产生交流电压输入信号的电池电压具有与振荡器电路所需的工作电压相反的极性，并且由输入电容器和整流器电路根据 交流电压信号。