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公开(公告)号：EP0190694B1
公开(公告)日：1991-06-12
申请号：EP86101353.0
申请日：1986-02-03
IPC分类号： H03M3/02
CPC分类号： H03M3/418 , H03M7/3022
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2.发明公开Method and apparatus for processing using neural network with reduced calculation amount 失效神经网络Netzwerksverarbeitungsverfahren und -Anlage mit reduzierter Berechnungsmenge
公开(公告)号：EP1033660A1
公开(公告)日：2000-09-06
申请号：EP00113124.2
申请日：1995-01-18
IPC分类号： G06F15/80
CPC分类号： G06N3/063 , G06N3/0481
摘要： A neural network circuit and a processing scheme using the neural network circuit in which a synapse calculation for each input value and a corresponding synapse weight of each input value which are expressed by binary bit sequences is carried out by using a sequentially specified bit of the corresponding synapse weight, a summation calculation for sequentially summing synapse calculation results for the input values is carried out to obtain a summation value, a prescribed nonlinear processing is applied to the obtained summation value so as to determine the output value, whether the obtained summation value reached to a saturation region of a transfer characteristic of the prescribed nonlinear processing is Judged, the synapse calculation and the summation calculation are controlled to sequentially carry out the synapse calculation from upper bits of the corresponding synapse weight, and to stop the synapse calculation and the summation calculation whenever it is Judged that the obtained summation value reached to the saturation region.
摘要翻译： 神经网络电路和使用神经网络电路的处理方案，其中通过二进制位序列表示的每个输入值的每个输入值和对应的突触权重的突触计算通过使用相应的 进行突触加权，进行用于顺序求和输入值的突触计算结果的求和计算，以获得求和值，对获得的求和值应用规定的非线性处理，以确定输出值，获得的求和值是否达到 判断为规定的非线性处理的传递特性的饱和区域，控制突触计算和求和计算，以依次对相应突触重量的高位进行突触计算，并停止突触计算和求和 每当计算出来的话就可以算了 ned求和值达到饱和区。
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公开(公告)号：EP0190694A3
公开(公告)日：1988-05-18
申请号：EP86101353
申请日：1986-02-03
IPC分类号： H03M03/02
CPC分类号： H03M3/418 , H03M7/3022
摘要： An oversampling converter includes first and second integrators for integrating a difference between an input terminal voltage and feedback voltages, first and second quantizers for quantizing outputs from the first and second integrators, respectively, first and second feedback paths for feeding back as the feedback voltages outputs from the first quantizer to the input sides of the first and second integrators, a differentiator arranged at an output side of the second quantizer, an adder for adding an output from the differentiator and the output from the first quantizer, and a circuit for supplying an output from the first integrator to an input terminal of the second integrator. Two or more quantization loops may be used. When the oversampling converter is used as an A/D converter, A/D converters are arranged in the first and second feedback paths. When the oversampling converter is used as a D/A converter, D/A converters are arranged between the adder and the first quantizer and between the adder and the second quantizer.
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公开(公告)号：EP0664516B1
公开(公告)日：2003-08-06
申请号：EP95100620.4
申请日：1995-01-18
IPC分类号： G06F15/80
CPC分类号： G06N3/063 , G06N3/0481
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公开(公告)号：EP0093644A2
公开(公告)日：1983-11-09
申请号：EP83400803.9
申请日：1983-04-22
发明人： Uchimura, Kuniharu , Iwata, Atsushi
CPC分类号： H03H19/00 , G11C27/024 , G11C27/026
摘要： In a switched capacitor circuit, in order to eliminate leakage of a power supply noise component to a signal line through an input capacitance of an operation amplifier, (1) an operating current of at least a first, differential stage among stages of the operational amplifier is regulated by a current regulation bias circuit, and (2) a power supply noise component having the same phase as that of an input signal is applied to the gate of a transistor of a gain stage, thereby stabilizing the operating point. In order to eliminate leakage of the power supply noise component to the signal line through a parasitic capacitance of an analog switch, (3) a dummy switch is used to detect a signal corresponding to the leakage component of the power supply noise component to the signal line, and an inverted signal having the opposite phase to that of the signal corresponding to the leakage component is applied to a substrate of the analog switch, thereby cancelling the actual leakage component.
摘要翻译： 在开关电容器电路中，为了通过运算放大器的输入电容消除电源噪声分量对信号线的泄漏，（1）运算放大器的各级中的至少第一差分级的工作电流 由电流调节偏置电路调节，并且（2）具有与输入信号相同相位的电源噪声分量被施加到增益级的晶体管的栅极，从而稳定工作点。 为了通过模拟开关的寄生电容消除电源噪声分量对信号线的泄漏，（3）使用虚拟开关来检测与电源噪声分量的泄漏分量对应的信号到信号 并且与模拟开关的基板相反的相反相位的反相信号被施加到模拟开关的基板，从而取消了实际的泄漏分量。
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公开(公告)号：EP0664516A3
公开(公告)日：1995-12-20
申请号：EP95100620.4
申请日：1995-01-18
IPC分类号： G06F15/80
CPC分类号： G06N3/063 , G06N3/0481
摘要： A neural network circuit and a processing scheme using the neural network circuit in which a synapse calculation for each input value and a corresponding synapse weight of each input value which are expressed by binary bit sequences is carried out by using a sequentially specified bit of the corresponding synapse weight, a summation calculation for sequentially summing synapse calculation results for the input values is carried out to obtain a summation value, a prescribed nonlinear processing is applied to the obtained summation value so as to determine the output value, whether the obtained summation value reached to a saturation region of a transfer characteristic of the prescribed nonlinear processing is judged, the synapse calculation and the summation calculation are controlled to sequentially carry out the synapse calculation from upper bits of the corresponding synapse weight, and to stop the synapse calculation and the summation calculation whenever it is judged that the obtained summation value reached to the saturation region.
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公开(公告)号：EP0477486A3
公开(公告)日：1993-07-21
申请号：EP91111435.3
申请日：1991-07-09
IPC分类号： G06F15/80
CPC分类号： G06K9/6287 , G06N3/063
摘要： A neural network circuit, in which a number n of weight coefficients (W1-wn) corresponding to a number n of inputs are provided, subtraction circuits determine the difference between inputs and the weight coefficients in each input terminal, the result thereof is inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients are inputted into an addition circuit and accumulated, and this accumulation result determines the output value. The threshold value circuit, which determines the final output value, has characteristics of a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can comprise simply EX-OR logic (exclusive OR) gates. Furthermore, in the case in which the input terminals have two input paths and two weight coefficients corresponding to each input path, the neuron circuits form a recognition area having a flexible shape which is controlled by the weight coefficients. Neuron circuits are widely used in pattern recognition; neuron circuits react to a pattern inputted into the input layer and recognition is thereby conducted.
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公开(公告)号：EP0477486A2
公开(公告)日：1992-04-01
申请号：EP91111435.3
申请日：1991-07-09
IPC分类号： G06F15/80
CPC分类号： G06K9/6287 , G06N3/063
摘要： A neural network circuit, in which a number n of weight coefficients (W1-wn) corresponding to a number n of inputs are provided, subtraction circuits determine the difference between inputs and the weight coefficients in each input terminal, the result thereof is inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients are inputted into an addition circuit and accumulated, and this accumulation result determines the output value. The threshold value circuit, which determines the final output value, has characteristics of a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can comprise simply EX-OR logic (exclusive OR) gates. Furthermore, in the case in which the input terminals have two input paths and two weight coefficients corresponding to each input path, the neuron circuits form a recognition area having a flexible shape which is controlled by the weight coefficients. Neuron circuits are widely used in pattern recognition; neuron circuits react to a pattern inputted into the input layer and recognition is thereby conducted.
摘要翻译： 一种神经网络电路，其中提供了对应于输入数量n的n个加权系数（W1-wn），减法电路确定每个输入端子中输入与加权系数之间的差值，其结果被输入到 绝对值电路，将与输入对应的绝对值电路的全部计算结果和权重系数输入到加法电路并进行累计，该累计结果决定输出值。 确定最终输出值的阈值电路具有阶梯函数图案，折线图案或S形函数图案的特性，取决于目标。 在通过数字电路实现神经网络电路的情况下，绝对值电路可以简单地包括EX-OR逻辑（异或）门。 此外，在输入端子具有对应于每个输入路径的两个输入路径和两个权重系数的情况下，神经元电路形成具有由权重系数控制的柔性形状的识别区域。 神经元电路广泛用于模式识别; 神经元电路对输入到输入层的图案起反应，从而进行识别。
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公开(公告)号：EP0275590A3
公开(公告)日：1989-01-18
申请号：EP87202532.5
申请日：1983-04-22
发明人： Uchimura, Kuniharu , Iwata, Atsushi
IPC分类号： G11C27/02
CPC分类号： H03H19/00 , G11C27/024 , G11C27/026
摘要： In a switched capacitor circuit, in order to eliminate leakage of a power supply noise component to a signal line through an input capacitance of an operation amplifier, a power supply noise component having the same phase as that of an input signal is applied to the gate of a transistor of a gain stage, thereby stabilizing the operating point. In order to eliminate leakage of the power supply noise component to the signal line through a parasitic capacitance of an analog switch, a dummy switch is used to detect a signal corresponding to the leakage component of the power supply noise component to the signal line, and an inverted signal having the opposite phase to that of the signal corresponding to the leakage component is applied to a substrate of the analog switch, thereby cancelling the actual leakage component.
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公开(公告)号：EP0477486B1
公开(公告)日：1996-05-01
申请号：EP91111435.3
申请日：1991-07-09
IPC分类号： G06F15/80
CPC分类号： G06K9/6287 , G06N3/063
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