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1.
公开(公告)号:EP1453206A1
公开(公告)日:2004-09-01
申请号:EP03026827.0
申请日:2003-11-20
IPC分类号: H03M1/08
CPC分类号: H03M3/502 , H03M1/0624 , H03M1/0872 , H03M1/742
摘要: A DAC including a first switch and a second switch. The first switch receives a digital signal to be converted, and the second switch receives the digital signal delayed by one-half of a clock signal. A third switch receives a current signal from a current source and the clock signal. The third switch alternately switches the current signal to the first and second switches so that when the clock signal is positive, the current signal is applied to the first switch and when the clock signal is zero, the current signal is applied to the second switch. The first switch will output the current signal during the first half of the clock cycle to a first output or a second output, and the second switch will output the current signal during the second half of the clock cycle to the first output or the second output.
摘要翻译: DAC,包括第一开关和第二开关。 第一开关接收要转换的数字信号,第二开关接收延迟时钟信号的二分之一的数字信号。 第三开关从电流源和时钟信号接收电流信号。 第三开关交替地将电流信号切换到第一和第二开关,使得当时钟信号为正时,电流信号被施加到第一开关,并且当时钟信号为零时,电流信号被施加到第二开关。 第一个开关将在时钟周期的前一半期间将当前信号输出到第一个输出或第二个输出,第二个开关将在时钟周期的后半段输出当前信号到第一个输出或第二个输出 。
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公开(公告)号:EP1453206B1
公开(公告)日:2006-10-18
申请号:EP03026827.0
申请日:2003-11-20
IPC分类号: H03M1/08
CPC分类号: H03M3/502 , H03M1/0624 , H03M1/0872 , H03M1/742
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